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1. 发明公开

KR20070081095A MULTIPROCESSOR SYSTEM AND BOOT-UP METHOD OF SLAVE SYSTEM 审中-公开
标题翻译：多处理器系统和从动系统的启动方法
公开(公告)号：KR20070081095A
公开(公告)日：2007-08-14
申请号：KR20070012747
申请日：2007-02-07
申请人： NEC ELECTRONICS CORP
发明人： UEMURA MARIKO , SUDA KEI
IPC分类号： G06F9/24
CPC分类号： G06F15/177 , G06F9/4405
摘要： A multiprocessor system and a method for booting a slave system are provided to reduce the number of components by not requiring the slave system having a program memory for storing a booting program and to simplify configuration of a loader by downloading the booting program through an inter-processor communication interface. The multiprocessor system includes the master system(10) and the slave system(20) connected to the master system through the inter-processor communication interface. The master system includes a program ROM(13) for storing the booting program for the slave system. The slave system includes the loader(25) for downloading the booting program from the program ROM of the master through the inter-processor communication interface. The loader includes a unit for transmitting confirming execution of a transmitted download command to a CPU(11) of the master system, and a storing unit for receiving and storing the booting program to a RAM(22).
摘要翻译：提供了一种用于引导从系统的多处理器系统和方法，用于通过不需要具有用于存储引导程序的程序存储器的从系统来简化组件的数量，并且通过下载引导程序来简化加载程序的配置。处理器通信接口。多处理器系统包括通过处理器间通信接口连接到主系统的主系统（10）和从系统（20）。主系统包括用于存储从系统的引导程序的程序ROM（13）。从系统包括用于通过处理器间通信接口从主机的程序ROM下载引导程序的加载程序（25）。该加载器包括用于向主系统的CPU（11）发送确认执行发送的下载命令的单元，以及用于接收并将引导程序存储到RAM（22）的存储单元。

2. 发明申请

WO2009118648A1 NETWORK SYSTEM OF TIME BAND RESERVATION, FRAME TRANSFER METHOD, AND NETWORK DEVICE 审中-公开
标题翻译：时间段预留网络系统，帧传送方法和网络设备
公开(公告)号：WO2009118648A1
公开(公告)日：2009-10-01
申请号：PCT/IB2009/005313
申请日：2009-03-26
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA , NEC ELECTRONICS CORPORATION , TAKEUCHI, Junichi , IGA, Naoto , GOTO, Hideki , IIYAMA, Shinichi
发明人： TAKEUCHI, Junichi , IGA, Naoto , GOTO, Hideki , IIYAMA, Shinichi
IPC分类号： H04L12/56 , H04L12/40
CPC分类号： H04W28/26 , H04L47/70 , H04L47/724 , H04L47/826
摘要： In a network system of this invention including a plurality of network devices that transfer frames by repeating, in a constant cycle, a reserved transfer interval that is a time band, in which a frame is transferred with a reservation and a free transfer interval that is a time band, in which a frame is freely transferred, a relay network device that links a first network device that is a transmission source of a frame and a second network device that is a transmission destination of the frame and the first network device execute a reservation processing such that the same time band within the reserved transfer interval is reserved and transfer the frame from the first network device to the second network device on the basis of the reservation result.
摘要翻译：在本发明的网络系统中，包括通过以恒定周期重复作为时间带的预约传送间隔来传送帧的多个网络设备，在该传输间隔中，以预约传输帧，并且自由传送间隔是可自由传送帧的时间带，将作为帧的发送源的第一网络装置和作为所述帧的发送目的地的第二网络装置进行链接的中继网络装置，并且所述第一网络装置执行预留处理，使得预留传送间隔内的相同时间段被保留，并且基于预留结果将帧从第一网络设备传送到第二网络设备。

3. 发明申请

WO2007102597A1 BROADBAND TRANSITION FROM A VIA INTERCONNECTION TO A PLANAR TRANSMISSION LINE IN A MULTILAYER SUBSTRATE 审中-公开
标题翻译：从多通道基板中的平面传输线的宽带连接过渡到宽带传输
公开(公告)号：WO2007102597A1
公开(公告)日：2007-09-13
申请号：PCT/JP2007/054621
申请日：2007-03-02
申请人： NEC CORPORATION , NEC Electronics Corporation , KUSHTA, Taras , NARITA, Kaoru , KANEKO, Tomoyuki , OGOU, Shin-ichi
发明人： KUSHTA, Taras , NARITA, Kaoru , KANEKO, Tomoyuki , OGOU, Shin-ichi
IPC分类号： H05K3/46
CPC分类号： H05K1/116 , H05K1/0219 , H05K1/0222 , H05K1/0245 , H05K1/0251 , H05K3/429 , H05K2201/09381 , H05K2201/09636 , H05K2201/09718 , H05K2201/09727
摘要： According to one embodiment, a broadband transition to joint a via structure and a planar transmission line in a multilayer substrate is formed as an intermediate connection between the signal via pad and the planar transmission line disposed at the same conductor layer. The transverse dimensions of the transition are equal to the via pad diameter at the one end and strip width at another end; The length of the transition can be equal to the characteristic dimensions of the clearance hole in the direction of the planar transmission line or defined as providing the minimal excess inductive reactance in time-domain according to numerical diagrams obtained by three-dimensional full-wave simulations.
摘要翻译：根据一个实施例，形成在多层基板中连接通孔结构和平面传输线的宽带转变，作为信号通孔焊盘和布置在相同导体层处的平面传输线之间的中间连接。过渡的横向尺寸等于一端的通孔焊盘直径和另一端的带宽度; 转换的长度可以等于平面传输线方向上的间隙孔的特征尺寸，或者定义为根据通过三维全波模拟获得的数值图在时域中提供最小的额外的电抗。

4. 发明申请

WO2006098498A1 DATA TRANSMITTING APPARATUS, DATA RECEIVING APPARATUS, COMMUNICATION SYSTEM, ERROR DETECTION METHOD AND PROGRAM 审中-公开
标题翻译：数据发送装置，数据接收装置，通信系统，错误检测方法和程序
公开(公告)号：WO2006098498A1
公开(公告)日：2006-09-21
申请号：PCT/JP2006/305753
申请日：2006-03-16
申请人： NEC ELECTRONICS CORPORATION , HATAGUCHI, Takeshi
发明人： HATAGUCHI, Takeshi
IPC分类号： H04L1/08
CPC分类号： H04L1/08
摘要： The fact that erroneous data has been received is sensed easily even if the data has been received at an erroneous timing on the receiving side. A data transmitting apparatus includes a digital computation circuit for subjecting digital data to be transmitted to n (where n is an integer of 2 or greater) different exclusive-OR computations, an authentication-data add-on circuit for gathering the n items of computed data into one set of data, and a data transmitting circuit for transmitting the set of data to a data receiving apparatus. A data receiving apparatus includes a digital reverse computation circuit for subjecting the n items of computed data, which have been received via a data receiving circuit, to respective ones of computations (exclusive-OR computations) that are the reverse of the digital computations on the transmitting side, and an authentication-data detecting circuit for detecting error in the receive data based upon degree of agreement among the n items of receive data obtained by the reverse computations.
摘要翻译：即使已经在接收侧的错误定时接收到数据，也容易感测到已经接收到错误数据的事实。数据发送装置包括数字计算电路，用于将数字数据发送到n（其中n是2或更大的整数）不同的异或运算;认证数据附加电路，用于收集计算出的n个项目数据转换为一组数据，以及数据发送电路，用于将数据集发送到数据接收装置。一种数据接收装置，包括一个数字反向计算电路，用于将已经经由数据接收电路接收到的n个计算数据项目对应于与数字计算相反的计算（异或运算）以及认证数据检测电路，用于根据通过反向计算获得的n个接收数据之间的一致度来检测接收数据中的错误。

5. 发明申请

WO2004090725A3 SECURE STORAGE SYSTEM WITH FLASH MEMORIES AND CACHE MEMORY 审中-公开
标题翻译：在Flash节能与高速缓存安全存储系统
公开(公告)号：WO2004090725A3
公开(公告)日：2005-09-15
申请号：PCT/EP2004003923
申请日：2004-04-14
申请人： NEC ELECTRONICS EUROP GMBH , POULARD FABRICE , NGUYEN VAN-LAM
发明人： POULARD FABRICE , NGUYEN VAN-LAM
IPC分类号： G06F12/02 , G06F12/08 , G06K19/07 , G07F7/10
CPC分类号： G07F7/1008 , G06F12/0802 , G06F12/0804 , G06F2212/2022 , G06K19/07 , G06Q20/341 , G06Q20/35765
摘要： The invention relates to a data-safe smart card device that, in addition to having a control unit (1001) and a flash memory (1003), comprised a non-volatile cache memory (1002), for example, provided in the form of an FeRAM or of an MRAM.
摘要翻译：本发明提出了在FeRAM中或MRAM的形式的数据安全的智能卡装置中，除了控制单元（1001）和闪速存储器（1003）具有内部非易失性高速缓冲存储器（1002），例如。

6. 发明申请

WO2005015850A1 DEVICE AND METHOD FOR DIAGNOSIS IN MULTI-CHANNEL-CAN-APPLICATIONS 审中-公开
标题翻译：用于诊断多通道CAN应用的设备和方法
公开(公告)号：WO2005015850A1
公开(公告)日：2005-02-17
申请号：PCT/EP2004/008595
申请日：2004-07-30
申请人： NEC ELECTRONICS (EUROPE) GMBH , WIEWESIEK, Wolfgang , YAKASHIRO, Masataka
发明人： WIEWESIEK, Wolfgang , YAKASHIRO, Masataka
IPC分类号： H04L12/413
CPC分类号： H04L12/4625 , H04L12/40032 , H04L12/4135 , H04L43/00 , H04L2012/40215
摘要： A CAN-network comprises several CAN-systems each having a CAN-bus and a CAN-interface which are connected to host-CPU by the CAN-bus. At least one CAN-interface is a selector interface which allows selective access to CAN-busses of other CAN-systems. Thereby it is possible to monitor data exchange on a bus by operating the selector interface in a so-called 'mirror mode' in which data of a monitored bus are automatically transferred to the bus of the selector interface. A connection to diagnosis units allows a diagnosis of the data exchange on the monitored bus.
摘要翻译： CAN网络包括几个CAN系统，每个CAN系统都有CAN总线和CAN接口，CAN总线通过CAN总线连接到主机CPU。至少有一个CAN接口是选择器接口，允许选择性地访问其他CAN系统的CAN总线。因此，可以通过以所谓的“镜像模式”操作选择器接口来监视总线上的数据交换，其中监视的总线的数据被自动传送到选择器接口的总线。与诊断单元的连接允许诊断监控总线上的数据交换。

7. 发明申请

WO2004030096A3 CRACK RESISTANT INTERCONNECT MODULE 审中-公开
标题翻译：抗裂纹互连模块
公开(公告)号：WO2004030096A3
公开(公告)日：2004-06-17
申请号：PCT/US0330060
申请日：2003-09-24
申请人： 3M INNOVATIVE PROPERTIES CO , NEC ELECTRONICS CORP
发明人： GORRELL ROBIN E , SYLVESTER MARK F , BANKS DONALD R , HOLCOMB MICHAEL D , BALLARD WILLIAM V , HIROSAWA KOUICHI , SATOU SADANOBU , KIMURA TERUHIKO
IPC分类号： H01L23/498
CPC分类号： H01L23/49822 , H01L23/49816 , H01L23/49894 , H01L2224/16 , H01L2224/73253 , H01L2924/01019 , H01L2924/01057 , H01L2924/01079 , H01L2924/15311 , H01L2924/16195 , H01L2924/3511
摘要： A laminated flip-chip interconnect package comprising a substrate having a chip attach surface and a board attach surface that define contact pads for attachment to corresponding pads on the chip and board wherein the substrate board surface comprises at least one solid plane covering the chip attach surface region near at least one chip corner. In one embodiment, the solid plane comprises a dielectric material, optionally covered with a soldermask or coverlay material. In an alternate embodiment, the solid plane comprises a metal, optionally covered with a soldermask or coverlay material.
摘要翻译：一种叠层倒装芯片互连封装，包括具有芯片附着表面和板附着表面的衬底，所述衬底附着表面限定用于附着到所述芯片和板上的相应焊盘的接触焊盘，其中所述衬底板表面包括覆盖所述芯片附着表面的至少一个实体平面区域靠近至少一个芯片角落。在一个实施例中，固体平面包括电介质材料，可选地用焊料掩模或覆盖层材料覆盖。在替代实施例中，固体平面包括金属，可选地用焊料掩模或覆盖层材料覆盖。

8. 发明申请

WO2004030096A2 CRACK RESISTANT INTERCONNECT MODULE 审中-公开
标题翻译：抗干扰互连模块
公开(公告)号：WO2004030096A2
公开(公告)日：2004-04-08
申请号：PCT/US2003/030060
申请日：2003-09-24
申请人： 3M INNOVATIVE PROPERTIES COMPANY , NEC ELECTRONICS CORPORATION
发明人： GORRELL, Robin, E. , SYLVESTER, Mark, F. , BANKS, Donald, R. , HOLCOMB, Michael, D. , BALLARD, William, V. , HIROSAWA, Kouichi , SATOU, Sadanobu , KIMURA, Teruhiko
IPC分类号： H01L23/498
CPC分类号： H01L23/49822 , H01L23/49816 , H01L23/49894 , H01L2224/16 , H01L2224/73253 , H01L2924/01019 , H01L2924/01057 , H01L2924/01079 , H01L2924/15311 , H01L2924/16195 , H01L2924/3511
摘要： A laminated flip-chip interconnect package comprising a substrate having a chip attach surface and a board attach surface that define contact pads for attachment to corresponding pads on the chip and board wherein the substrate board surface comprises at least one solid plane covering the chip attach surface region near at least one chip corner. In one embodiment, the solid plane comprises a dielectric material, optionally covered with a soldermask or coverlay material. In an alternate embodiment, the solid plane comprises a metal, optionally covered with a soldermask or coverlay material.
摘要翻译：一种层压倒装芯片互连封装，包括具有芯片连接表面的基板和限定用于连接到芯片和板上的相应焊盘的接触焊盘的板附着表面，其中基板表面包括覆盖芯片连接表面的至少一个实心平面区域至少有一个芯片角落。在一个实施例中，固体平面包括电介质材料，任选地覆盖有焊接掩模或覆盖材料。在替代实施例中，固体平面包括可选地用焊接掩模或覆盖物材料覆盖的金属。

9. 发明申请

WO03096378A8 DISPLAY DRIVER IC, DISPLAY MODULE AND ELECTRICAL DEVICE INCORPORATING A GRAPHICS ENGINE 审中-公开
标题翻译：显示驱动IC，显示模块和并入图形引擎的电气设备
公开(公告)号：WO03096378A8
公开(公告)日：2004-02-19
申请号：PCT/IB0302356
申请日：2003-05-09
申请人： NEC ELECTRONICS CORP , BITBOYS OY , KOSELJ METOD , TUOMI MIKA
发明人： KOSELJ METOD , TUOMI MIKA
IPC分类号： G06T1/00 , G06T1/20 , G06T11/00 , G06T11/20 , G06T11/40 , G06T15/00 , G09G3/36 , G09G5/00 , G09G5/399 , H01L20060101 , H01L21/00 , H01L
CPC分类号： G06T11/203 , G06T1/20 , G06T11/40 , G06T15/005 , G06T2200/12 , G09G3/3611
摘要： The invention provides a display driver integrated circuit, for connection to a small-area display, the integrated circuit including a hardware-implemented graphics engine for receiving vector graphics commands and rendering image data for display pixels in dependence upon the received commands, and also including display driver circuitry for driving the connected display in accordance with the image data rendered by the graphics engine. In another aspect the graphics engine is held within the display module, but not embedded in the display driver IC. The invention provides graphics acceleration that increases display performance, but does not significantly increase cost of manufacture. Power consumption in comparison to non-accelerated CPU graphics processing is lowered.
摘要翻译：本发明提供了一种用于连接到小区域显示器的显示驱动器集成电路，该集成电路包括用于接收矢量图形命令的硬件实现的图形引擎，并且根据所接收的命令来渲染用于显示像素的图像数据，并且还包括显示驱动器电路，用于根据由图形引擎呈现的图像数据来驱动连接的显示器。在另一方面，图形引擎保持在显示模块内，但不嵌入在显示驱动器IC中。本发明提供了增加显示性能但不显着增加制造成本的图形加速度。与非加速CPU图形处理相比，功耗降低。

10. 发明申请

WO2009118653A1 NETWORK DEVICE PERFORMING CONNECTION CHECK, NETWORK SYSTEM, AND FRAME TRANSFER METHOD 审中-公开
标题翻译：网络设备执行连接检查，网络系统和帧传输方法
公开(公告)号：WO2009118653A1
公开(公告)日：2009-10-01
申请号：PCT/IB2009/005439
申请日：2009-03-26
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA , NEC ELECTRONICS CORPORATION , TAKEUCHI, Junichi , IGA, Naoto , GOTO, Hideki , IIYAMA, Shinichi
发明人： TAKEUCHI, Junichi , IGA, Naoto , GOTO, Hideki , IIYAMA, Shinichi
IPC分类号： H04L12/64 , H04L12/46 , H04J3/06
CPC分类号： H04L12/40091 , H04J3/0652 , H04L12/40078 , H04L12/4035 , H04L12/462
摘要： A network device that transfers frames by repeating, in a constant cycle, a reserved transfer interval that is a time band, in which a frame is transferred with a reservation, and a free transfer interval that is a time band, in which a frame is freely transferred, includes: a BPDU generation unit (146) that generates a first BPDU; and a BPDU transmission instruction unit (143) that instructs to arrange the first BPDU in the reserved transfer interval and transmit the first BPDU to a first other network device.
摘要翻译：一种网络设备，其通过以恒定周期重复作为其中帧的传送与预留的时间带的保留传送间隔和作为帧的时间段的自由传送间隔来传送帧，帧的间隔是包括：产生第一BPDU的BPDU生成单元（146）; 以及BPDU发送指示单元，其指示将所述第一BPDU布置在所述预留传送间隔中，并将所述第一BPDU发送到第一其他网络设备。

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