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1. 发明授权

US07813466B2 Jitter-free divider 有权
标题翻译：无抖动分频器
公开(公告)号：US07813466B2
公开(公告)日：2010-10-12
申请号：US12405905
申请日：2009-03-17
申请人： Yu Huang , Wei Fu
发明人： Yu Huang , Wei Fu
IPC分类号： H03K21/00
CPC分类号： H03K23/68
摘要： A system and method are provided for jitter-free fractional division. The method accepts a first plurality of first signal phases, each phase having a first frequency. To make the division jitter-free, a phase is selected subsequent to deselecting a previous phase selection. The selected phase is divided by the integer N, supplying a second signal with a second frequency. Using the second signal as a clock, a first plurality of counts is triggered in series, and the counts are used to select a corresponding phase. The first signal may separate neighboring phases by 90 degrees. Then, for (N+0.25), a first count triggers a second count and selects the first phase, the second count triggers a third count and selects the second phase, the third count triggers a fourth count and selects the third phase, and the fourth count trigger the first count and selects the fourth phase.
摘要翻译：提供了一种用于无抖动分数除法的系统和方法。该方法接受第一多个第一信号相位，每个相位具有第一频率。为了使分频无抖动，在取消选择先前的相位选择之后选择相位。所选择的相位除以整数N，提供具有第二频率的第二信号。使用第二信号作为时钟，串联地触发第一多个计数，并且使用计数来选择相应的相位。第一个信号可以将相邻相位分离90度。然后，对于（N + 0.25），第一计数触发第二计数并选择第一相位，第二计数触发第三计数并选择第二相位，第三计数触发第四计数并选择第三相，并且第四计数触发第一个计数并选择第四个阶段。

2. 发明授权

US08248170B2 Stabilized digital quadrature oscillator 有权
标题翻译：稳定数字正交振荡器
公开(公告)号：US08248170B2
公开(公告)日：2012-08-21
申请号：US12952154
申请日：2010-11-22
申请人： Dariush Dabiri , Dongwoon Bai , Nils Graef , Wenwei Pan
发明人： Dariush Dabiri , Dongwoon Bai , Nils Graef , Wenwei Pan
IPC分类号： H03K3/03
CPC分类号： G06F1/022
摘要： A stabilized quadrature oscillator providing consistently high signal quality is disclosed. The stabilized quadrature oscillator includes an iterative quadrature oscillator and a quadrature signal stabilizer. The iterative quadrature oscillator generates an iterative cosine signal and an iterative sine signal using a stabilized cosine signal and a stabilized sine signal from the quadrature signal stabilizer. The quadrature signal stabilizer generates the stabilized cosine signal and the stabilized sine signal based on an energy measure of the iterative cosine signal and the iterative sine signal. Specifically, if the energy measure is less than a low threshold then the quadrature signal stabilizer generates the stabilized sine signal and the stabilized cosine signal to have a greater magnitude than the iterative sine signal and the iterative cosine signal, respectively. Conversely, if the energy measure is greater than a high threshold then the quadrature signal stabilizer generates the stabilized sine signal and the stabilized cosine signal to have a lesser magnitude than the iterative sine signal and the iterative cosine signal, respectively.
摘要翻译：公开了一种提供一致的高信号质量的稳定的正交振荡器。稳定的正交振荡器包括迭代正交振荡器和正交信号稳定器。迭代正交振荡器使用稳定余弦信号和来自正交信号稳定器的稳定正弦信号产生迭代余弦信号和迭代正弦信号。正交信号稳定器基于迭代余弦信号和迭代正弦信号的能量测量值产生稳定的余弦信号和稳定的正弦信号。具体地说，如果能量测量小于低阈值，则正交信号稳定器分别产生稳定的正弦信号和稳定的余弦信号，以具有比迭代正弦信号和迭代余弦信号更大的幅度。相反，如果能量测量值大于高阈值，则正交信号稳定器分别产生稳定正弦信号和稳定余弦信号，其幅度分别小于迭代正弦信号和迭代余弦信号。

3. 发明授权

US07382788B2 Method and apparatus for implementing a data frame processing model 有权
标题翻译：用于实现数据帧处理模型的方法和装置
公开(公告)号：US07382788B2
公开(公告)日：2008-06-03
申请号：US10435214
申请日：2003-05-08
申请人： Scott Furey , Salil Suri , Michael Moretti , Thomas Wu , David Geddes
发明人： Scott Furey , Salil Suri , Michael Moretti , Thomas Wu , David Geddes
IPC分类号： H04L12/28
CPC分类号： H04L69/22
摘要： A method and apparatus for bridging network protocols is disclosed. In one embodiment, a data frame is received and stored in a dual-port memory queue by hardware logic. An embedded processor is notified of the data frame once a programmable number of bytes of the data frame have been received and stored. Once notified, the embedded processor may then undertake to read the data frame from the memory queue while the hardware logic is still writing to the memory queue. In one embodiment, the processor may then translate the data frame's protocol and begin transmitting it out over a network connection, all while the data frame's payload is still being received.
摘要翻译：公开了一种桥接网络协议的方法和装置。在一个实施例中，数据帧被硬件逻辑接收并存储在双端口存储器队列中。一旦数据帧的可编程数量的字节已经被接收和存储，嵌入式处理器就被通知数据帧。一旦通知，当硬件逻辑仍在写入存储器队列时，嵌入式处理器然后可以承担从存储器队列读取数据帧。在一个实施例中，处理器然后可以转换数据帧的协议，并且开始通过网络连接发送它，同时数据帧的有效载荷仍在被接收。

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