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1. 发明申请

WO2005010889A1 FLASH/DYNAMIC RANDOM ACCESS MEMORY FIELD PROGRAMMABLE GATE ARRAY 审中-公开
标题翻译：闪存/动态随机存取现场可编程门阵列
公开(公告)号：WO2005010889A1
公开(公告)日：2005-02-03
申请号：PCT/US2004/022556
申请日：2004-07-13
申请人： ACTEL CORPORATION , MCCOLLUM, John , BELLIPPADY, Vidya , BAKKER, Gregory
发明人： MCCOLLUM, John , BELLIPPADY, Vidya , BAKKER, Gregory
IPC分类号： G11C7/00
CPC分类号： G11C11/406
摘要： A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.
摘要翻译：用于选择性地互连集成电路器件中的两个节点的电路包括具有多个字线和多个位线的存储器阵列。刷新晶体管具有耦合到多个位线之一的源极，耦合到动态随机存取存储器字线和漏极的控制栅极。开关晶体管具有耦合到刷新晶体管的漏极的栅极，耦合到节点中的第一节点的源极和耦合到节点中的第二节点的漏极。地址解码器，用于向字线和动态随机存取存储器字线提供周期性信号。

2. 发明申请

WO1996021273A2 TWO-TRANSISTOR ZERO-POWER ELECTRICALLY-ALTERABLE NON-VOLATILE LATCH 审中-公开
标题翻译：双转子零电压可变电压非易失性锁存器
公开(公告)号：WO1996021273A2
公开(公告)日：1996-07-11
申请号：PCT/US1996000306
申请日：1996-01-04
申请人： ACTEL CORPORATION
发明人： ACTEL CORPORATION , KOWSHIK, Vikram
IPC分类号： H03K03/356
CPC分类号： H03K17/24 , H01L27/115 , H03K3/356008
摘要： A two-transistor, zero-power, electrically-alterable non-volatile latch element comprises an input node, an output node, and an erase node. A P-Channel MOS transistor has a source connected to a source of first electrical potential, a drain connected to the output node, a control gate connected to the input node, and a floating gate capacitively coupled to the control gate. An N-Channel MOS transistor has a source connected to a source of second electrical potential lower than the first electrical potential, a drain connected to the output node, a control gate connected to the input node, and a floating gate capacitively coupled to the control gate and electrically connected to the floating gate of the P-Channel MOS transistor. The floating gates of the P-Channel MOS transistor and the N-Channel MOS transistor are capacitively coupled to the erase node via a tunnel dielectric.
摘要翻译：双晶体管零功率可电可变非易失性锁存元件包括输入节点，输出节点和擦除节点。 P沟道MOS晶体管具有连接到第一电位源的源极，连接到输出节点的漏极，连接到输入节点的控制栅极和电容耦合到控制栅极的浮动栅极。 N沟道MOS晶体管具有连接到低于第一电位的第二电位源的源极，连接到输出节点的漏极，连接到输入节点的控制栅极，以及电容耦合到控制器的浮动栅极栅极并电连接到P沟道MOS晶体管的浮置栅极。 P沟道MOS晶体管和N沟道MOS晶体管的浮置栅极经由隧道电介质电容耦合到擦除节点。

3. 发明申请

WO2006138086A3 NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT 审中-公开
公开(公告)号：WO2006138086A3
公开(公告)日：2006-12-28
申请号：PCT/US2006/021569
申请日：2006-06-01
申请人： ACTEL CORPORATION , DHAOUI, Fethi , MCCOLLUM, John , BELLIPPADY, Vidyadhara , WANG, Zhigang
发明人： DHAOUI, Fethi , MCCOLLUM, John , BELLIPPADY, Vidyadhara , WANG, Zhigang
IPC分类号： H01L29/788
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch- transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

4. 发明申请

WO2006071555A2 ESD PROTECTION STRUCTURE FOR I/O PAD SUBJECT TO BOTH POSITIVE AND NEGATIVE VOLTAGES 审中-公开
标题翻译：针对两个正负电压的I / O平台的ESD保护结构
公开(公告)号：WO2006071555A2
公开(公告)日：2006-07-06
申请号：PCT/US2005/045522
申请日：2005-12-16
申请人： ACTEL CORPORATION , BAKKER, Gregory
发明人： BAKKER, Gregory
IPC分类号： H01L23/62
CPC分类号： H01L27/0266
摘要： An ESD protection circuit is disclosed for an n-channel MOS transistor formed in an inner p-well of a triple-well process and connected to an I/O pad that may experience both positive and negative voltages according to the present invention. A first switch connects the p-well containing the n-channel MOS transistor to ground if the voltage at the I/O pad is positive and a second switch connects the p-well containing the n-channel MOS transistor to the I/O pad if the voltage at the I/O pad is negative. A third switch connects the gate of the n-channel MOS transistor to the p-well if it is turned off and a fourth switch connects the gate of the n-channel MOS transistor to V cc if it is turned on.
摘要翻译：公开了一种ESD保护电路，用于形成在三阱工艺的内部p阱中的n沟道MOS晶体管，并连接到根据本发明可以经历正和负电压的I / O焊盘。如果I / O焊盘的电压为正，则第一开关将包含n沟道MOS晶体管的p阱连接到地，而第二开关将包含n沟道MOS晶体管的p阱连接到I / O焊盘如果I / O焊盘的电压为负。第三开关将n沟道MOS晶体管的栅极连接到p阱，如果它是关断的，并且第四开关将n沟道MOS晶体管的栅极连接到V cc cc 打开。

5. 发明申请

WO2006039254A3 FACE TO FACE BONDED I/O CIRCUIT DIE AND FUNCTIONAL LOGIC CIRCUIT DIE SYSTEM 审中-公开
公开(公告)号：WO2006039254A3
公开(公告)日：2006-04-13
申请号：PCT/US2005/034526
申请日：2005-09-26
申请人： ACTEL CORPORATION , SPEERS, Theodore
发明人： SPEERS, Theodore
IPC分类号： H01L23/48
摘要： An integrated circuit system includes a first set of integrated circuit dice each member of the set having a different configuration of input/output circuits disposed thereon and a second set of integrated circuit dice each having different logical function circuits disposed thereon. Each member of the first and second sets of integrated circuit dice include an array of face-to-face bonding pads disposed thereon that mate with the array of face-toface bonding pads of each member of the other set.

6. 发明申请

WO1997050176A1 MULTIPLE LOGIC FAMILY COMPATIBLE OUTPUT DRIVER 审中-公开
标题翻译：多种逻辑家庭兼容的输出驱动器
公开(公告)号：WO1997050176A1
公开(公告)日：1997-12-31
申请号：PCT/US1997010683
申请日：1997-06-20
申请人： ACTEL CORPORATION
发明人： ACTEL CORPORATION , PLANTS, William, C. , BAKKER, Gregory, W.
IPC分类号： H03K19/0185
CPC分类号： H03K19/018521
摘要： An output buffer circuit (10) connected to an I/O pad (18) of the integrated circuit, includes an output totem pole (12), a level shifter (14) and enable logic (16). The output totem pole (12) has a first input connected to the level shifter (14) and a second input connected to the enable logic (16) and an output connected to the I/O pad (18), and includes a pullup transistor (22) connected to 3.3 volt Vcc and a pulldown transistor (20) connected to ground. In a first embodiment, totem pole pullup transistor (22) is an N-channel MOS transistor turned on by a 5-volt signal from the level shifter (14), and in a second embodiment, it is a P-channel MOS transistor formed in an N-well tied to the 5-volt Vcc, and turned on by a ground level signal from the level shifter (14). The enable logic (16) inputs are a Data input, a Global enable input and an Output enable input.
摘要翻译：连接到集成电路的I / O焊盘（18）的输出缓冲电路（10）包括输出图腾柱（12），电平移位器（14）和使能逻辑（16）。输出图腾柱（12）具有连接到电平移位器（14）的第一输入和连接到使能逻辑（16）的第二输入和连接到I / O焊盘（18）的输出，并且包括上拉晶体管（22）连接到3.3伏Vcc和连接到地的下拉晶体管（20）。在第一实施例中，图腾柱上拉晶体管（22）是通过来自电平移位器（14）的5伏特信号导通的N沟道MOS晶体管，在第二实施例中，它是形成的P沟道MOS晶体管在与5伏Vcc相连的N阱中，并且由来自电平移位器（14）的地电平信号导通。使能逻辑（16）输入是数据输入，全局使能输入和输出使能输入。

7. 发明申请

WO1996041374A1 DOUBLE HALF VIA ANTIFUSE 审中-公开
标题翻译：双重通过抗体
公开(公告)号：WO1996041374A1
公开(公告)日：1996-12-19
申请号：PCT/US1996007989
申请日：1996-05-29
申请人： ACTEL CORPORATION
发明人： ACTEL CORPORATION , McCOLLUM, John, L.
IPC分类号： H01L23/525
CPC分类号： H01L21/76888 , H01L23/5252 , H01L23/53223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An antifuse (10) comprises a substantially planar conductive lower electrode (14) covered by a first layer of silicon nitride. A layer of amorphous silicon (16) is disposed over the silicon nitride layer. A first dielectric layer (18) is disposed over the surface of the amorphous silicon layer (16) and has a first aperture therethrough communicating with the amorphous silicon layer. A second layer of silicon nitride (22) is disposed over the first dielectric layer (18) and in the first aperture. A conductive upper electrode (20), such as a layer of titanium nitride, is disposed over the second layer (22) of silicon nitride. A second dielectric layer (22) is disposed over the surface of the conductive upper electrode (20) and has a second aperture therethrough in alignment with the first aperture communicating with the conductive upper electrode (20). An overlying metal layer (24) is disposed over the surface of the second dielectric layer (22) and in the second aperture making electrical contact with the conductive upper electrode (20).
摘要翻译：反熔丝（10）包括由第一氮化硅层覆盖的基本平面的导电下电极（14）。非晶硅层（16）设置在氮化硅层上。第一介电层（18）设置在非晶硅层（16）的表面上方，并且具有与非晶硅层连通的第一孔。第二层氮化硅（22）设置在第一介电层（18）上和第一孔中。诸如氮化钛层的导电上电极（20）设置在氮化硅的第二层（22）之上。第二电介质层（22）设置在导电上电极（20）的表面上方，并且具有通过其与与导电上电极（20）连通的第一孔对准的第二孔。覆盖金属层（24）设置在第二电介质层（22）的表面上，并且在与导电上电极（20）电接触的第二孔中。

8. 发明申请

WO1996039717A1 REDUCED LEAKAGE ANTIFUSE STRUCTURE AND FABRICATION METHOD 审中-公开
标题翻译：降低抗漏电抗结构和制造方法
公开(公告)号：WO1996039717A1
公开(公告)日：1996-12-12
申请号：PCT/US1996009235
申请日：1996-06-05
申请人： ACTEL CORPORATION
发明人： ACTEL CORPORATION , McCOLLUM, John, L. , HAWLEY, Frank, W.
IPC分类号： H01L23/525
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An antifuse (10) comprises an antifuse material (24) disposed between a lower conductive electrode (14) and an upper conductive electrode (26). The antifuse material (24) comprises a layer of amorphous silicon (20) disposed between two layers of silicon nitride (16, 20). A thin layer of silicon dioxide (18) is disposed between the layer of amorphous silicon (20) and one of the silicon nitride layers (16, 22).
摘要翻译：反熔丝（10）包括设置在下导电电极（14）和上导电电极（26）之间的反熔丝（24）。反熔丝材料（24）包括设置在两层氮化硅（16,20）之间的非晶硅层（20）。二氧化硅薄层（18）设置在非晶硅层（20）和氮化硅层（16,22）之一之间。

9. 发明申请

WO1996038861A1 RAISED TUNGSTEN PLUG ANTIFUSE AND FABRICATION PROCESS 审中-公开
标题翻译：提高TUNGSTEN PLUG抗体和制造工艺
公开(公告)号：WO1996038861A1
公开(公告)日：1996-12-05
申请号：PCT/US1996008263
申请日：1996-05-31
申请人： ACTEL CORPORATION
发明人： ACTEL CORPORATION , HAWLEY, Frank, W. , McCOLLUM, John, L. , GO, Ying , ELTOUKHY, Abdelshafy
IPC分类号： H01L23/525
CPC分类号： H01L23/5252 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An antifuse (10) comprises a lower electrode (14) formed from a metal layer in a microcircuit (12). An interlayer dielectric layer (16) is disposed over the lower electrode (14) and has an aperture formed therein. A conductive plug, formed from a material such as tungsten, is formed in the aperture. The upper surface of the interlayer dielectric (16) is etched back to create a raised portion of the plug (18). The upper edges of the plug (18) are rounded. An antifuse layer (24), preferably comprising a silicon nitride, amorphous silicon, silicon nitride sandwich incorporating a thin silicon dioxide layer (28) above or below the amorphous silicon layer (24) or such a sandwich structure covered by a titanium nitride layer, is disposed above the plug (18). An upper electrode (34), preferably comprising a metal layer is disposed over the antifuse layer (24).
摘要翻译：反熔丝（10）包括在微电路（12）中由金属层形成的下电极（14）。层间绝缘层（16）设置在下电极（14）的上方并具有形成在其中的孔。在孔中形成由诸如钨的材料形成的导电插塞。层间电介质（16）的上表面被回蚀以形成插头（18）的凸起部分。插头（18）的上边缘是圆形的。一种反熔丝层（24），优选地包括氮化硅，非晶硅，包含在非晶硅层（24）上方或下方的薄二氧化硅层（28）的氮化硅夹层或由氮化钛层覆盖的夹层结构，设置在插头（18）上方。优选地包括金属层的上电极（34）设置在反熔丝层（24）的上方。

10. 发明申请

WO2009029542A1 CORNER I/O PAD DENSITY 审中-公开
标题翻译：拐角I / O密度
公开(公告)号：WO2009029542A1
公开(公告)日：2009-03-05
申请号：PCT/US2008/074098
申请日：2008-08-22
申请人： ACTEL CORPORATION , BAKKER, Gregory, W. , GREENE, Jonathan, W.
发明人： BAKKER, Gregory, W. , GREENE, Jonathan, W.
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/06179 , H01L2224/48091 , H01L2224/49171 , H01L2224/85399 , H01L2924/00014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01076 , H01L2924/01082 , H01L2924/14 , H01L2224/45099
摘要： An integrated circuit die has a plurality of I/O cells disposed about its periphery, each I/O cell having an I/O bonding pad. A first group of I/O cells is disposed at the periphery of the die at locations away from corners of the die, each of the first group of I/O cells having an I/O pad disposed thereon and spaced at a first distance from the periphery of the die. A second group of I/O cells is disposed at the periphery of the die at locations away from corners of the die, each of the second group of I/O cells having an I/O pad disposed thereon and spaced at a distance from the periphery of the die more than the first distance, the distance increasing as a function of the proximity of each I/O cell to a corner of the die.
摘要翻译：集成电路管芯具有围绕其周边设置的多个I / O单元，每个I / O单元具有I / O焊盘。第一组I / O单元设置在远离模具角部的位置处的管芯周边处，第一组I / O单元中的每一个具有设置在其上的I / O焊盘，并且间隔开第一距离模具的周边。第二组I / O单元设置在离芯片的角部的位置处的管芯周边处，第二组I / O单元中的每一个具有设置在其上的间隔开的距离，模具的周边大于第一距离，该距离随着每个I / O单元与模具角落的接近程度的增加而增加。

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