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81. 实用新型

CN207218667U 一种卫星导航时间修正装置失效
公开(公告)号：CN207218667U
公开(公告)日：2018-04-10
申请号：CN201720813656.4
申请日：2017-07-06
申请人：江汉大学
发明人：罗会容
IPC分类号： H03L7/097
摘要：本实用新型涉及原子钟技术领域，具体涉及一种卫星导航时间修正装置，包括温控模块连接VCXO，VCXO分别连接DDS分频模块、压控修正模块、增益控制模块和传统电子线路，传统电子线路连接量子系统，压控修正模块连接伺服电路，DDS分频模块连接相位累积模块，相位累积模块连接GPS信号接收机；增益控制模块与压控修正模块相连，量子系统依次连接伺服电路、相位累积模块。该修正装置分频后的信号频率与同步参考信号频率一致，实现同频不同相位的检测，以提高检测精度。

82. 发明专利

DE60033204T2 未知
公开(公告)号：DE60033204T2
公开(公告)日：2007-05-03
申请号：DE60033204
申请日：2000-03-29
申请人： FUJITSU LTD
发明人： SEGAWA YUJI , OTSUKA MASARU , KIKUCHI OSAMU , HAGA AKIRA , YOSHIKAWA YOSHINORI
IPC分类号： H03K3/0231 , H03L7/097 , H03K3/03 , H03K5/08 , H03K5/24 , H03K19/00 , H03K19/003
摘要： A voltage controller oscillator circuit includes first and second chopper comparators (120,121), a capacitor (122), first and second current sources (123,124) and a converter circuit (125) for making the current sources (123,124) to generate a current (I) proportionate to an input voltage (Vin). The voltage controlled oscillator circuit further includes first and second switches (126,127) and an inverter (128) for controlling on/off of the current sources (123,124). A logic circuit (129) latches the output signals of the comparators (120,121), outputs the output voltage (Vout) that serves as an oscillation signal of the voltage controlled oscillator and generates clock signals ( phi 1, phi 2) for switching operation of the chopper comparators (120,121).

83. 发明专利

AU2006292011A1 A method and apparatus adapted to demodulate a data signal 未知
公开(公告)号：AU2006292011A1
公开(公告)日：2007-03-22
申请号：AU2006292011
申请日：2006-09-08
申请人： MAGELLAN TECH PTY LTD
发明人： MURDOCH GRAHAM ALEXANDER MUNRO , LITTLECHILD STUART COLIN
IPC分类号： H04B5/00 , H03D1/24 , H03L7/097

84. 发明专利

DE19954696A1 未知
公开(公告)号：DE19954696A1
公开(公告)日：2001-05-17
申请号：DE19954696
申请日：1999-11-13
申请人： PHILIPS CORP INTELLECTUAL PTY
发明人： BENING ANDREAS , KEMPF PETER , WALTERS ECKHARD
IPC分类号： H03L7/08 , H03L7/06 , H03L7/18 , H04B1/40 , H04J3/06 , H04L7/033 , H04Q7/32 , H03K5/15 , H03L7/097
摘要： The device has a clock generator unit (2) with an input (10) for a reference clock with an electric circuit containing a phase control loop (4) for converting the reference clock into a working clock. The circuit has stages (16a,16b) for different reference clocks and each stage can be selected Independent claims are also included for the following: a method of generating a working clock, especially for a mobile system.

85. 发明专利

CA2260456A1 A FREQUENCY-LOCKED LOOP WITH GATED REFERENCE AND VCO INPUTS 未知
公开(公告)号：CA2260456A1
公开(公告)日：2000-07-27
申请号：CA2260456
申请日：1999-01-27
申请人： PHILSAR ELECTRONICS INC
发明人： CLOUTIER MARK MILES , CHERRY JAMES ANDREW , SWAMINATHAN ASHOK
IPC分类号： H03D11/02 , H03D13/00 , H03L7/089 , H03L7/14 , H03L7/18 , H04L27/00 , H04L27/02 , H03L7/097 , H03L7/083
摘要： Disclosed is a frequency-locked loop (FLL), which attempts to bring about frequency and phase synchronization between two signals over the control bandwidth of the loop: a reference signal and a voltage-controlled oscillator (VCO) signal. A preferred embodiment of the invention employs a reference signal generated by a crystal oscillator of frequency f REF (possibly reduced in frequency by dividing by a factor R), and a VCO signal generated by the oscillations of an unquenched SRG resonator (possibly passed through a limiting amplifier) with tunable resonant frequency f RES (possibly reduced in frequency by dividing by a factor N). These (possibly divided-down) signals are connected to the inputs of a phase/frequency detector (PFD). A PFD a circuit which compares the phases of two digital input signals, denoted "R" and "V" for "reference" and "VCO"; if a reference rising edge precedes a VCO rising edge, an "up" pulse denoted "U" is generated, while a VCO edge preceding a reference edge generates a "down" ("D") pulse. These pulses are used to control the current sources in a charge-pump circuit whose net current is applied to a loop filter (LF) which creates a voltage using some kind of charge-storage element. This loop filter voltage is a so-called error voltage whose value is used to control the frequency of the resonator; the combination of PFD, charge pump, and LF is connected such that the error voltage is controlled to bring the reference signal and VCO signal into phase synchrony.

86. 发明专利

DE69021566D1 未知
公开(公告)号：DE69021566D1
公开(公告)日：1995-09-14
申请号：DE69021566
申请日：1990-05-17
申请人： MOTOROLA INC
发明人： MARTIN FREDERICK
IPC分类号： H03K5/26 , G01R25/00 , H03D13/00 , H03L7/085 , H03L7/087 , H03L7/097 , H03K9/06

87. 发明专利

CS550488A3 ULTRASONIC GENERATOR CIRCUITRY 未知
公开(公告)号：CS550488A3
公开(公告)日：1992-11-18
申请号：CS550488
申请日：1988-08-08
申请人： SATRONIC AG
发明人： KONRAD MANFRED
IPC分类号： B05B17/06 , B06B1/02 , H03L7/00 , H03L7/097 , B06B1/06
摘要： A method and a circuit for exciting an ultrasonic generator comprises a control loop which includes the ultrasonic generator itself and a voltage-controlled oscillator. The control loop keeps the active power consumption to a desired value, which is compared in a comparator with the instantaneous active power consumption. One output of a further rectangular oscillator is connected to the control input of the voltage-controlled oscillator. The rectangular oscillator is put into operation if in the control loop there are no control oscillations or only those which are smaller than a predetermined threshold. The output of the rectangular oscillator is connected across one diode to the control input of the voltage-controlled oscillator and across another diode to the controlled input of comparator. The additional signal is applied to the voltage-controlled oscillator, apart from the control signal of the control loop. The cycle of the additional signal is longer than the change time constant at the control input of the voltage-controlled oscillator and the additional signal swing is selected in such a way that the frequency of oscillator passes through a predetermined frequency range.

88. 发明专利

DE2844936C2 未知
公开(公告)号：DE2844936C2
公开(公告)日：1983-05-26
申请号：DE2844936
申请日：1978-10-16
申请人： LICENTIA PATENT-VERWALTUNGS-GMBH, 6000 FRANKFURT, DE
发明人： MALINOWSKI, CHRISTOPH, DR.-ING. , RINDERLE, HEINZ, ING.(GRAD.), 7100 HEILBRONN, DE
IPC分类号： H03G1/02 , A63H30/04 , G01R23/00 , G01R23/06 , H03J9/00 , H03L7/06 , H03L7/097 , H04Q9/10

89. 发明专利

DE2844936A1 Simple remote control for TV or radio receiver - has converter producing DC voltage dependent on ratio of two frequencies 未知
公开(公告)号：DE2844936A1
公开(公告)日：1980-04-17
申请号：DE2844936
申请日：1978-10-16
申请人： LICENTIA GMBH
发明人： MALINOWSKI CHRISTIOPH DR ING , RINDERLE HEINZ ING GRAD
IPC分类号： H03G1/02 , A63H30/04 , G01R23/00 , G01R23/06 , H03J9/00 , H03L7/06 , H03L7/097 , H04Q9/10 , H04Q9/00
摘要： The remote control has a converter, a control and an oscillator connected into a control loop. The control consists of a comparator or operational amplifier and a signal source. A reference signal source is also present. The converter is supplied with the reference signal and with the oscillator output. The converter is designed so that it produces a dc component dependent on the ratio of the frequency of the oscillator's output signal and the reference signal. This dependency may be proportionality or it may follow a specified equation.

90. 发明专利

CA2374777C CLOCK/DATA RECOVERY CIRCUIT 未知
公开(公告)号：CA2374777C
公开(公告)日：2004-05-25
申请号：CA2374777
申请日：2002-03-06
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： ICHINO HARUHIKO , KISHINE KEIJI
IPC分类号： H03L7/08 , H04J3/04 , H04L7/033 , H04L7/027 , H03L7/097
摘要： A clock/data recovery circuit used in a receiving apparatus is provided in the circuit including: a voltage control oscillator for generating a clock signal of a frequency of 1/K of a bit rate of an input data signal; a delay circuit; a demultiplexer for demultiplexing the input data signal; a multiplexer for multiplexing the demultiplexed signals; a phase comparator for comparing phases of an output signal of the delay circuit and an output signal of the multiplexer; a lowpass filter; wherein the clock/data recovery circuit outputs the clock signal generated by the voltage control oscillator as a recovery divided clock signal, and outputs the demultiplexed signals output as recovery parallel data signals.

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