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1. 发明专利

CA2260456A1 A FREQUENCY-LOCKED LOOP WITH GATED REFERENCE AND VCO INPUTS 未知
公开(公告)号：CA2260456A1
公开(公告)日：2000-07-27
申请号：CA2260456
申请日：1999-01-27
申请人： PHILSAR ELECTRONICS INC
发明人： CLOUTIER MARK MILES , CHERRY JAMES ANDREW , SWAMINATHAN ASHOK
IPC分类号： H03D11/02 , H03D13/00 , H03L7/089 , H03L7/14 , H03L7/18 , H04L27/00 , H04L27/02 , H03L7/097 , H03L7/083
摘要： Disclosed is a frequency-locked loop (FLL), which attempts to bring about frequency and phase synchronization between two signals over the control bandwidth of the loop: a reference signal and a voltage-controlled oscillator (VCO) signal. A preferred embodiment of the invention employs a reference signal generated by a crystal oscillator of frequency f REF (possibly reduced in frequency by dividing by a factor R), and a VCO signal generated by the oscillations of an unquenched SRG resonator (possibly passed through a limiting amplifier) with tunable resonant frequency f RES (possibly reduced in frequency by dividing by a factor N). These (possibly divided-down) signals are connected to the inputs of a phase/frequency detector (PFD). A PFD a circuit which compares the phases of two digital input signals, denoted "R" and "V" for "reference" and "VCO"; if a reference rising edge precedes a VCO rising edge, an "up" pulse denoted "U" is generated, while a VCO edge preceding a reference edge generates a "down" ("D") pulse. These pulses are used to control the current sources in a charge-pump circuit whose net current is applied to a loop filter (LF) which creates a voltage using some kind of charge-storage element. This loop filter voltage is a so-called error voltage whose value is used to control the frequency of the resonator; the combination of PFD, charge pump, and LF is connected such that the error voltage is controlled to bring the reference signal and VCO signal into phase synchrony.

2. 发明专利

CA2290862C A FREQUENCY/PHASE COMPARISON CIRCUIT WITH GATED REFERENCE AND SIGNAL INPUTS 未知
公开(公告)号：CA2290862C
公开(公告)日：2004-05-11
申请号：CA2290862
申请日：1999-11-25
申请人： PHILSAR ELECTRONICS INC
发明人： CLOUTIER MARK MILES , SWAMINATHAN ASHOK , CHERRY JAMES ANDREW
IPC分类号： H03D13/00 , H03L7/089 , H03L7/099 , H03L7/14 , H03L7/18 , H04L27/00 , H04L27/02 , G01R23/14 , H03L7/091 , H04B1/26
摘要： Disclosed is a frequency-locked loop (FLL), which attempts to bring abo ut frequency and phase synchronization between two signals over the control bandwidth of the loop: a reference signal and a voltage-controlled oscillato r (VCO) signal. For example, the FLL employs a reference signal generated by a crystal oscillator of frequency .function. REF and a VCO signal generated by the oscillations of an unquenched SRG resonator with tunable resonant frequency .function. RE S. These signals are connected to the inputs of a phase/frequency detector (PFD) whic h produces output pulses in response to the relationship between .function.REF and .function.RES. These pulses are applied to a loop filter (LF) which creates a voltage using some kind of charge-storage element. This loop filter voltage is a so-called error voltag e whose value is used to control the frequency of the resonator to bring the referen ce signal and VCO signal into phase synchrony.

3. 发明专利

CA2290862A1 A FREQUENCY/PHASE COMPARISON CIRCUIT WITH GATED REFERENCE AND SIGNAL INPUTS 未知
公开(公告)号：CA2290862A1
公开(公告)日：2000-07-27
申请号：CA2290862
申请日：1999-11-25
申请人： PHILSAR ELECTRONICS INC
发明人： SWAMINATHAN ASHOK , CLOUTIER MARK MILES , CHERRY JAMES ANDREW
IPC分类号： H03D13/00 , H03L7/089 , H03L7/099 , H03L7/14 , H03L7/18 , H04L27/00 , H04L27/02 , G01R23/14 , H03L7/091 , H04B1/26
摘要： Disclosed is a frequency-locked loop (FLL), which attempts to bring about frequency and phase synchronization between two signals over the control bandwidth of the loop: a reference signal and a voltage-controlled oscillator (VCO) signal. For example, the FLL employs a reference signal generated by a crystal oscillator of frequency ~REF and a VCO signal generated by the oscillations of an unquenched SRG resonator with tunable resonant frequency ~RES. These signals are connected to the inputs of a phase/frequency detector (PFD) which produces output pulses in response to the relationship between ~REF and ~RES. These pulses are applied to a loop filter (LF) which creates a voltage using some kind of charge-storage element. This loop filter voltage is a so-called error voltage whose value is used to control the frequency of the resonator to bring the reference signal and VCO signal into phase synchrony.

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