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81. 发明授权

US3886005A Method of manufacturing semiconductor devices 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US3886005A
公开(公告)日：1975-05-27
申请号：US37904673
申请日：1973-07-13
申请人： MOTOROLA INC
发明人： COTA MARLO E , OSBORNE JOHN F
IPC分类号： H01L21/00 , H01L21/3065 , H01L21/74 , H01L21/761 , H01L21/8222 , H01L7/34
CPC分类号： H01L21/8222 , H01L21/00 , H01L21/3065 , H01L21/74 , H01L21/761 , Y10S148/007 , Y10S148/015 , Y10S148/037 , Y10S148/085 , Y10S148/102 , Y10S148/145
摘要： A method of making semiconductor devices using selective impurity diffusion techniques. A dopant layer of a first conductivity type is formed on a semiconductor body of a second conductivity type. A patterned photoresist layer is formed on the dopant layer to mask portions thereof, and an etchant is used to remove the exposed area of the dopant layer in the unmasked areas, exposing the semiconductor body thereat. A thin layer of the semiconductor body is removed at the exposed areas by being subjected to a plasma etchant in a plasma reactor. The photoresist is removed by substituting oxygen for the plasma etchant in the plasma reactor. The semiconductor is then heated to diffuse a region of said second conductivity type into the semiconductor. A protective oxide coating may be provided on the exposed silicon prior to the diffusion step to prevent autodoping. The protective oxide coating and the dopant layer are removed. The delineation provided by the plasma etching step may be used as an aid in subsequent mask alignment steps.
摘要翻译：使用选择性杂质扩散技术制造半导体器件的方法。在第二导电类型的半导体本体上形成第一导电类型的掺杂剂层。在掺杂剂层上形成图案化的光致抗蚀剂层以掩盖其部分，并且使用蚀刻剂去除未掩蔽区域中的掺杂剂层的暴露区域，从而在其上暴露半导体主体。通过在等离子体反应器中经受等离子体蚀刻剂，在暴露的区域去除半导体体的薄层。通过用等离子体反应器中的等离子体蚀刻剂取代氧来去除光致抗蚀剂。然后加热半导体以使所述第二导电类型的区域扩散到半导体中。在扩散步骤之前，可以在暴露的硅上提供保护性氧化物涂层以防止自动掺杂。去除保护性氧化物涂层和掺杂剂层。通过等离子体蚀刻步骤提供的描绘可以用于辅助在随后的掩模对准步骤中。

82. 发明授权

US3844858A Process for controlling the thickness of a thin layer of semiconductor material and semiconductor substrate 失效
标题翻译：用于控制薄层半导体材料和半导体衬底的厚度的方法
公开(公告)号：US3844858A
公开(公告)日：1974-10-29
申请号：US78816768
申请日：1968-12-31
申请人： TEXAS INSTRUMENTS INC
发明人： BEAN K
IPC分类号： H01L21/00 , H01L21/304 , H01L21/306 , H01L21/762 , H01L7/50
CPC分类号： H01L21/76297 , H01L21/00 , Y10S148/049 , Y10S148/051 , Y10S148/085 , Y10S148/102 , Y10S148/115 , Y10S438/977
摘要： Process permitting control of the thickness of the thin layer of semiconductor material by first forming a slot of a predetermined depth in one surface so that the slot will be exposed during removal of material from the opposite surface should the thickness of the thin layer of semiconductor material become less than the depth of the slot, and a (110) oriented semiconductor substrate having a slot formed therein which is bounded by converging (111) planes. In a preferred embodiment the thickness control is realized by first preparing the slice of semiconductor material so that at least one of its surfaces has a (100) orientation. There is then formed on the surface of the slice having the (100) orientation an etch-resistant mask having a window opened therethrough such that the window defines on the surface of the slice two lines which are parallel to each other and to lines defined by the intersection of (111) planes with the surface of the slice. Semiconductor material is then removed through the windows by etching to produce a slot having a depth greater than thickness to which the single crystal semiconductor material is to be subsequently processed. A vapor deposited support layer may then be produced on the surface of the slice to which the mask was attached during which process it will fill the slot etched in the semiconductor material through the window. Upon removal of the semiconductor material from the opposite surface of the slice, which may be affected by lapping and polishing, the support layer formed in the slot will become exposed, thus indicating that the thickness of the semiconductor material remaining is equal to or less than the depth of the slot etched in the first surface of the semiconductor material. At the time the first depth control slot is formed in the first surface of the semiconductor slice, there may also be performed a plurality of similar slots, the depth of which are controlled by controlling the width of the window in the etch resistant mask. Thus, as semiconductor material is removed from the slice, the thickness of the material remaining after the removal process can be determined by the number of slots exposed during lapping and polishing.
摘要翻译：工艺允许通过首先在一个表面上形成预定深度的槽来控制半导体材料薄层的厚度，使得如果半导体材料薄层的厚度应该从相对表面去除材料期间露出槽变得小于槽的深度，并且其中形成有槽的（110）取向的半导体衬底由{111}平面收敛而界定。

83. 发明授权

US3808527A Alignment determining system 失效
标题翻译：对准测定系统
公开(公告)号：US3808527A
公开(公告)日：1974-04-30
申请号：US37429673
申请日：1973-06-28
申请人： IBM
发明人： THOMAS D
IPC分类号： H01L21/66 , G01R31/28 , H01L21/50 , G01R27/02
CPC分类号： G01R31/2853 , Y10S148/102 , Y10S438/975
摘要： Method and apparatus for electrically measuring the alignment between a first design or element on an object such as a wafer and a second design or element formed by, e. g., a mask superimposed on the object or wafer. The design on the wafer may be at least one resistive point in a resistive area in or on the wafer and the design formed by the mask may be at least one contact point in at least one contact located in one or more apertures of the mask and disposed on the resistive area. The resistive area is preferably an elongated resistor having a pair of spaced points defining a known distance between which a voltage is determined after passing a current through the resistor or resistive area. Voltages between selected combinations of the points is determined. The misalignment, if any, is calculated from these voltages and the known distance between the pair of spaced points.
摘要翻译：用于电测量诸如晶片的物体上的第一设计或元件与第二设计或元件之间的对准的方法和装置，例如叠加在物体或晶片上的掩模。晶片上的设计可以是晶片中或晶片上的电阻区域中的至少一个电阻点，并且由掩模形成的设计可以是位于掩模的一个或多个孔中的至少一个触点中的至少一个接触点，以及设置在电阻区域上。电阻区域优选地是具有限定已知距离的一对间隔点的细长电阻器，在该距离之间通过电流通过电阻器或电阻区域之后确定电压。确定点的选定组合之间的电压。根据这些电压和一对间隔点之间的已知距离计算未对准（如果有的话）。

84. 发明授权

US3783044A Photoresist keys and depth indicator 失效
标题翻译：光电子和深度指示器
公开(公告)号：US3783044A
公开(公告)日：1974-01-01
申请号：US3783044D
申请日：1971-04-09
申请人： MOTOROLA INC
发明人： CHESKIS E , PRICE J
IPC分类号： H01L21/00 , H01L21/762 , H01L23/544 , H01L7/50 , H01L5/00 , H01L7/00
CPC分类号： H01L23/544 , H01L21/00 , H01L21/76297 , H01L2223/54453 , H01L2223/54493 , H01L2924/0002 , Y10S148/05 , Y10S148/051 , Y10S148/085 , Y10S148/102 , Y10S148/115 , Y10S438/975 , Y10S438/977 , H01L2924/00
摘要： A METHOD IS DISCLOSED FOR PROVIDING MEANS FOR ORIENTING AND POSITIONING A PHOTORESIST MASK ON A SEMICONDUCTOR WAFER AND FOR INDICATING THE DEPTH OF AN EPITAXIAL DEPOSIT. THIS MEANS COMPRISES FILLED HOLES CALLED KEYS WHICH ARE EASILY NOTED EVEN THOUGH THE SURFACE OF THE WAFER IS CAREFULLY POLISHED. SINCE THE DEPTH OF THE KEYS IS LESS BY A PREDETERMINED AMOUNT THAN THE DEPTH OF THE EPITAXIAL DEPOSIT, PRESENCE OF THE DEYS AFTER THE POLISHING STEP INDICATES THAT THE REMAINING DEPTH OF THE DEPOSIT IS GREAT ENOUGH TO MAKE APPLICATION OF OTHER PROCESS STEPS TO THE WAFER ADVISALBE AND THE KEYS THEMSELVES ARE USED FOR POSITIONING AND ORIENTING SUCH FIXTURES AS MASKING DEVICES ON THE SURFACE OF THE WAFER.

D R A W I N G

85. 发明授权

US3752702A Method of making a schottky barrier device 失效
标题翻译：制造肖特基阻挡器件的方法
公开(公告)号：US3752702A
公开(公告)日：1973-08-14
申请号：US3752702D
申请日：1969-09-29
申请人： IIZUKA M , HOSHIDA O , KANO G , FUJIWARA S , IWASA H , TERAMOTO I , HASEGAWA H
发明人： KANO G , HASEGAWA H , TERAMOTO I , IWASA H , HOSHIDA O , FUJIWARA S , IIZUKA M
IPC分类号： C23F1/02 , C23F1/40 , H01L21/00 , H01L21/306 , H01L23/485 , H01L29/47 , H01L29/872 , B28D5/00 , H01L7/50
CPC分类号： H01L21/00 , C23F1/02 , C23F1/40 , H01L21/30608 , H01L23/485 , H01L2924/0002 , Y10S148/051 , Y10S148/102 , Y10S148/115 , Y10S148/139 , Y10T428/24917 , H01L2924/00
摘要： AN ETCHING PROCESS FOR ORIENTED SILICON SUBSTRATE ALONG A HEXAGONAL WINDOW, IN WHICH AN ETCHED RECESS IS FORMED ALONG THE WINDOW IN A CLEAR SHAPE BY MEANS OF DIRECTING ONE SIDE OF THE HEXAGONAL WINDOW PARALLEL TO A CRYSTALLOGRAPHIC AXIS OR . A METAL IS THEN FORMED IN THE ETCHED RECESS TO FORM THE SCHOTTKY BARRIER BETWEEN THE METAL AND THE SEMICONDUCTOR MATERIAL BY DEPOSITING SAID METAL BY MEANS OF THE SPUTTERING OR VACUUM EVAPORATION METHOD. A VACANT SPACE IS THEREBY FORMED JUST UNDER AN INSULATING FILM ALONG THE PREIPHERY OF THE WINDOW, RESULTING IN A SCHOTTKY BARRIER DEVICE HAVING A GOOD BACKWARD CHARACTERISTIC.

86. 发明授权

US3728166A Semiconductor device fabrication method and product thereby 失效
标题翻译：半导体器件制造方法和产品
公开(公告)号：US3728166A
公开(公告)日：1973-04-17
申请号：US3728166D
申请日：1967-01-11
申请人： IBM
发明人： BARDELL P , PECORARO R , BARSON F , BENJAMIN C
IPC分类号： H01L21/00 , H01L21/8222 , H01L29/00 , H01L7/34 , B01J17/00
CPC分类号： H01L21/00 , H01L21/8222 , H01L29/00 , Y10S148/037 , Y10S148/085 , Y10S148/102 , Y10S148/106 , Y10S148/115 , Y10S438/975
摘要： PATTERN. THIS PERMITS ACCURATE ALIGNMENT THAT IS NECESSARY FOR ANY SUBSEQUENT PROCESS OPERATION, WUCH AS DIFFUSION, TO BE ACCURATELY PERFORMED THEREBY INCREASING THE YIELD IN THE MANUFACTURE OF, FOR EXAMPLE, INTEGRAATED SEMICONDUCTOR DEVICES.

THIS IS A METHOD FOR ERLIABLY REPRODUCING, ON THE SURFACE OF AN EPITAXIALLY GROWN MONOCRYATALLINE LAYER, A PATTERN THAT WAS FORMED ON THE SURFACE OF THE SUBSTRATE ON WHICH THE EPITAXIAL LAYER WAS GROWN. BY USING A SUBSTRATE HAVING A (100.) CRYSTALLOGRAPHIC ORIENTATION, THE (100.) EPITAXIAL GROWN LAYER REPRODUCES THE PATTERN ON THE SUBSTRATE SURFACE DIRECTLY ABOVE THE SUBSTRATE SURFACE

87. 发明授权

US3679497A Electron beam fabrication system and process for use thereof 失效
公开(公告)号：US3679497A
公开(公告)日：1972-07-25
申请号：US3679497D
申请日：1969-10-24
申请人： WESTINGHOUSE ELECTRIC CORP
发明人： HANDY ROBERT M , ANGELLO STEPHEN J , MALMBERG PAUL R , O'KEEFFE TERENCE W
IPC分类号： H01L21/027 , F15C5/00 , G01Q30/08 , G03F7/20 , H01J37/302 , H01L21/00 , H01L23/29 , B44C1/22 , B23P1/00 , H01J37/26
CPC分类号： H01L21/00 , F15C5/00 , H01J37/3023 , H01L23/293 , H01L2924/0002 , Y10S148/026 , Y10S148/05 , Y10S148/051 , Y10S148/102 , Y10S204/06 , Y10S428/901 , Y10S438/949 , H01L2924/00
摘要： A SYSTEM FOR FABRICATION OF PATTERNS IS SUBSTRATES SUCH AS INTERGRATED CIRCUITS ON SILICON WAFERS, EMPLOYS A SCANNING ELECTRON MICROSCOPE TO PRODUCE A PHOTOCATHODE HAVING THE DESIRED SURFACE PATTERN THEREIN AND THE PHOTCATHODE IS THEN EMPLOYED TO PRODUCE REPLICATE PATTERNS ON A PLURALITY OF SUBSTRATES. THE PHOTOCATHODE PRODUCES A PATTERNED ELECTRON BEAM WHICH IMPINGES ON AN ELECTRON RESIST ON A SUBSTRATE TO PROVIDE FOR DIFFERENTIAL SOLUBILITY BETWEEN THE ELECTRON BEAM TTREATED ZND UNTREATED RESIST AREAS. REMOVING THE MORE SOLUBLE PORTION OF THE ELECTRON RESIST AFTER TREATMENT BY THE PHOTOCATHODE, EXPOSES THE SUBSTRATE SURFACE WHICH IS THEN ALTERED EITHER PHYSICALLY OR CHEMICALLY. ONE OR MORE HIGHLY PRECISE PATTERNS BOTH IN THEIR LOCATION AND CONFIGURATION, MAY BE PRODUCED ON THE SURFACE OF A SUBSTRATE BY APPLYING A SERIES OF SUCCESSIVE ELECTRON RESISTS TO THE SUBSTRATE AND USING A PLURALITY OF PHOTOCATHODES.

88. 发明授权

US3624463A Method of and apparatus for indicating semiconductor island thickness and for increasing isolation and decreasing capacity between islands 失效
标题翻译：用于指示半导体岛厚度和增加岛屿隔离度和降低能力的方法和装置
公开(公告)号：US3624463A
公开(公告)日：1971-11-30
申请号：US3624463D
申请日：1969-10-17
申请人： MOTOROLA INC
发明人： DAVIDSOHN URYON SAHARI
IPC分类号： H01L21/762 , H01L27/06 , H01L19/00
CPC分类号： H01L27/0652 , H01L21/76297 , Y10S148/051 , Y10S148/085 , Y10S148/102 , Y10S148/122
摘要： The thickness of a single crystal island, which forms part of a slab of material, is indicated by the number of lines appearing on the surface of the slab. Since the lines are edges of thin layers of an insulating material, the insulating layer or layers also act to isolate the single crystal islands from each other and also to reduce the capacity between the islands.

89. 发明授权

US3379584A Semiconductor wafer with at least one epitaxial layer and methods of making same 失效
标题翻译：具有至少一个外延层的半导体晶片及其制造方法
公开(公告)号：US3379584A
公开(公告)日：1968-04-23
申请号：US39440864
申请日：1964-09-04
申请人： TEXAS INSTRUMENTS INC
发明人： BEAN KENNETH E , RUNYAN WALTER R
IPC分类号： H01L21/761 , H01L21/8222 , H01L27/06 , H01L27/07
CPC分类号： H01L21/8222 , H01L21/761 , H01L27/0658 , H01L27/0772 , Y10S148/035 , Y10S148/037 , Y10S148/051 , Y10S148/085 , Y10S148/102 , Y10S148/115 , Y10S148/145 , Y10S438/975

90. 发明授权

US3192844A Mask alignment fixture 失效
标题翻译：面罩对准夹具
公开(公告)号：US3192844A
公开(公告)日：1965-07-06
申请号：US26298163
申请日：1963-03-05
申请人： KULICKE AND SOFFA MFG COMPANY
发明人： SZASZ PETER R , KULICKE JR FREDERICK W , ALBERT SOFFA
IPC分类号： H01L21/68
CPC分类号： H01L21/682 , Y10S101/36 , Y10S148/102 , Y10T29/53261

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