专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明申请

US20150149675A1 MEMORY CONTROLLER, INFORMATION PROCESSING APPARATUS, AND METHOD OF CONTROLLING MEMORY CONTROLLER 有权
标题翻译：记忆控制器，信息处理装置和控制存储器控制器的方法
公开(公告)号：US20150149675A1
公开(公告)日：2015-05-28
申请号：US14542730
申请日：2014-11-17
申请人： FUJITSU LIMITED
发明人： Yuta Toyoda , Koji HOSOE , AKIO TOKOYODA , Masatoshi Aihara , Makoto SUGA
IPC分类号： G06F13/16 , G06F13/366
CPC分类号： G06F13/1605 , G06F13/161 , G06F13/366
摘要： A memory controller has a request holding unit holding a write request and a read request; a transmission unit transmitting any one of the write request and the read request to a memory through a transmission bus; a reception unit receiving read data corresponding to the read request through a reception bus; and a request arbitration unit performing: a first processing of transmitting the write request before the read request, when a first reception time is not later than a second reception time, and a second processing of transmitting the read request before the write request, when the first reception time is later than the second reception time. The first reception time is when reception of the read data is started when the write request is transmitted first, and the second reception time is when the reception of the read data is started when the read request is transmitted first.
摘要翻译：存储器控制器具有保持写请求和读请求的请求保持单元; 发送单元，通过发送总线将写入请求和读取请求中的任一个发送到存储器; 接收单元，通过接收总线接收对应于读取请求的读取数据; 以及请求仲裁单元，执行：当第一接收时间不晚于第二接收时间时，在所述读取请求之前发送所述写入请求的第一处理，以及在所述写入请求之前发送所述读取请求的第二处理，第一接收时间晚于第二接收时间。第一接收时间是当首先发送写请求时开始读取数据的接收，并且第二接收时间是当首先发送读取请求时开始读取数据的接收。

82. 发明申请

US20140169381A1 Unified system Networking with PCIE-CEE Tunneling 有权
标题翻译：具有PCIE-CEE隧道的统一系统网络
公开(公告)号：US20140169381A1
公开(公告)日：2014-06-19
申请号：US14138697
申请日：2013-12-23
申请人： International Business Machines Corporation
发明人： Casimer M. DeCusati , Rajaram B. Krishnamurthy
IPC分类号： H04L12/46 , G06F13/366
CPC分类号： H04L45/66 , G06F13/366 , G06F13/387 , G06F2213/0026 , H04L12/413 , H04L12/4633
摘要： Peripheral Component Interconnect Express (PCIe) tunneling over Converged Enhanced Ethernet (CEE) networks. The CEE networks comprise devices configured to use PCIe. An initiating device initiates a command. The command is associated with initiator control signals, which are associated with the initiating device. The initiating device requests permission from an arbiter, and receives a request grant from the arbiter. Based on the request grant, a mapping device maps the initiator control signals, an target device address, and the command into a CEE control frame. Based on the mapping, the initiating device transmits an inquiry to the devices. Based on transmitting the inquiry, the initiating device receives a response from a corresponding device. The corresponding device is associated with the target device address. The response comprises target control signals associated with the corresponding device. Based on the response, the initiating device initiates a transaction to the corresponding device through CEE control frames.
摘要翻译：通过融合增强型以太网（CEE）网络的外围组件互连Express（PCIe）隧道。 CEE网络包括配置为使用PCIe的设备。启动设备启动命令。该命令与与启动设备相关联的启动器控制信号相关联。启动设备请求仲裁器的许可，并从仲裁器接收请求许可。基于请求授权，映射设备将发起者控制信号，目标设备地址和命令映射到CEE控制帧中。基于映射，发起设备向设备发送查询。基于发送查询，发起设备从对应的设备接收响应。相应的设备与目标设备地址相关联。响应包括与相应设备相关联的目标控制信号。基于响应，启动设备通过CEE控制帧发起对相应设备的事务。

83. 发明授权

US08683114B2 Device security features supporting a distributed shared memory system 有权
标题翻译：支持分布式共享内存系统的设备安全功能
公开(公告)号：US08683114B2
公开(公告)日：2014-03-25
申请号：US13238989
申请日：2011-09-21
申请人： Joseph R. M. Zbiciak , Amitabh Menon
发明人： Joseph R. M. Zbiciak , Amitabh Menon
IPC分类号： G06F13/00
CPC分类号： G06F12/1483 , G06F12/14 , G06F12/1425 , G06F12/1433 , G06F12/1441 , G06F12/1458 , G06F12/1491 , G06F13/366 , G06F21/78 , G06F21/79 , G06F2212/1052 , Y02D10/14
摘要： A memory management and protection system that incorporates device security features that support a distributed, shared memory system. The concept of secure regions of memory and secure code execution is supported, and a mechanism is provided to extend a chain of trust from a known, fixed secure boot ROM to the actual secure code execution. Furthermore, the system keeps a secure address threshold that is only programmable by a secure supervisor, and will only allow secure access requests that are above this threshold.
摘要翻译：内存管理和保护系统，其中集成了支持分布式共享内存系统的设备安全功能。支持存储器和安全代码执行的安全区域的概念，并且提供了一种机制来将信任链从已知的固定安全引导ROM扩展到实际的安全代码执行。此外，系统保持仅由安全监督程序编程的安全地址阈值，并且将仅允许高于该阈值的安全访问请求。

84. 发明申请

US20130086586A1 Issuing Requests To A Fabric 有权
公开(公告)号：US20130086586A1
公开(公告)日：2013-04-04
申请号：US13248276
申请日：2011-09-29
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Kar Leong Wong , Robert P. Adler
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Kar Leong Wong , Robert P. Adler
IPC分类号： G06F9/46
CPC分类号： G06F13/4221 , G06F13/366 , G06F13/368 , G06F13/4022 , G06F15/7807 , G06F15/7864
摘要： In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed.

85. 发明申请

US20070204081A1 BUS SYSTEM AND METHOD FOR OPERATING A BUS SYSTEM 有权
标题翻译：总线系统和操作总线系统的方法
公开(公告)号：US20070204081A1
公开(公告)日：2007-08-30
申请号：US11678872
申请日：2007-02-26
申请人： Karl Herz
发明人： Karl Herz
IPC分类号： G06F13/00
CPC分类号： G06F13/366
摘要： A method for operating a bus system, in particular in a microprocessor or microcontroller, and a semiconductor device for performing the method is disclosed. In one embodiment, for optimizing the order of accesses to the bus system, a method for operating a bus system includes at least one transmission channel, wherein the transmission channel connects at least two masters and at least one slave with one another. The masters are connected with an arbiter determining the order of accesses in which the masters access the transmission channel. The method provides that the arbiter takes into account meta information about planned accesses when determining the order of accesses. Meta information can further be stored and be referred to for subsequent determinations.
摘要翻译：公开了一种用于操作总线系统的方法，特别是在微处理器或微控制器中，以及用于执行该方法的半导体器件。在一个实施例中，为了优化对总线系统的访问顺序，用于操作总线系统的方法包括至少一个传输信道，其中传输信道将至少两个主设备和至少一个从设备彼此连接起来。主机与确定主机访问传输通道的访问顺序的仲裁器连接。该方法规定，仲裁器在确定访问顺序时，会考虑有关计划访问的元信息。元信息可以进一步存储并被引用用于随后的确定。

86. 发明授权

US06976106B2 Method and apparatus for speculative response arbitration to improve system latency 有权
标题翻译：用于推测应答仲裁以提高系统延迟的方法和装置
公开(公告)号：US06976106B2
公开(公告)日：2005-12-13
申请号：US10286721
申请日：2002-11-01
申请人： Jay S. Tomlinson , Chien-Chun Chou
发明人： Jay S. Tomlinson , Chien-Chun Chou
IPC分类号： G06F13/36 , G06F13/366
CPC分类号： G06F13/366
摘要： A method and apparatus for speculative response arbitration to improve system latency have been described.
摘要翻译：已经描述了用于推测应答仲裁以提高系统延迟的方法和装置。

87. 发明授权

US06337619B1 Method of selecting an electronic module from a plurality of modules present in the interrogation field of a terminal 有权
标题翻译：从存在于终端的询问字段中的多个模块中选择电子模块的方法
公开(公告)号：US06337619B1
公开(公告)日：2002-01-08
申请号：US09187517
申请日：1998-11-06
申请人： Jacek Kowalski , Bruno Charrat , Eric Bouyoux , Michel Martin
发明人： Jacek Kowalski , Bruno Charrat , Eric Bouyoux , Michel Martin
IPC分类号： H04Q522
CPC分类号： G06K7/10059 , G06F13/366 , G06K7/0008
摘要： A method for selecting an electronic module from a plurality of at least two modules (M1, M2, M3) capable of emitting messages simultaneously, includes the steps of sending a general query message (ACTIVALL) to the modules, and selecting (AFI, SELECT-ID) the module having responded first, the modules, on receiving a query message (ACTIVALL, ACTIV), determining a random time interval (P) and sending a responding message (ID, R) when the said time interval (P) has elapsed. A module is set in idle position (IDL) when it receives a message (MESS) before the time interval (P) preceding the sending of a response (ID, R) has elapsed. The idle position (IDL) is at least characterized by the fact that one module does not respond, subsequently, to a complementary query message (ACTIV). This invention is particularly useful for contactless smart card readers and for terminals for electronic labels.
摘要翻译：一种用于从能够同时发送消息的多个至少两个模块（M1，M2，M3）中选择电子模块的方法，包括以下步骤：向模块发送一般查询消息（ACTIVALL），并选择（AFI，SELECT -ID）所述模块首先响应，所述模块在接收到查询消息（ACTIVALL，ACTIV）时，确定随机时间间隔（P）并在所述时间间隔（P）具有的时间间隔（P））时发送响应消息（ID，R）过去。当在发送响应（ID，R）之前的时间间隔（P）之前接收到消息（MESS）时，模块被设置为空闲位置（IDL）。至少空闲位置（IDL）的特征在于一个模块不响应于补充查询消息（ACTIV）。本发明对于非接触式智能卡读取器和用于电子标签的终端特别有用。

88. 发明授权

US5696912A Multi-media computer architecture 失效
标题翻译：多媒体计算机体系结构
公开(公告)号：US5696912A
公开(公告)日：1997-12-09
申请号：US684337
申请日：1996-07-19
申请人： Robert P. Bicevskis , Adrian H. Hartog , Gordon Caruk , Michael A. Alford
发明人： Robert P. Bicevskis , Adrian H. Hartog , Gordon Caruk , Michael A. Alford
IPC分类号： G06F3/14 , G06F13/366 , G06F13/38
CPC分类号： G06F3/14 , G06F13/366 , G09G2340/02 , G09G2340/125
摘要： A computer system is comprised of at least one of a main bus and an attached expansion bus, a CPU connected to the main bus, peripherals connected to one of the main bus or to the expansion buses, a subsystem connected to a bus for receiving control, address and data signals from the CPU comprising a graphics controller, a data compression circuit, a video controller, a memory connected to data input ports of the circuits and controllers via a subsystem bus having a bandwidth sufficient to carry video and graphics display signals, a first arbiter for determining which controller is permitted access the memory, a link bus connecting each of the controllers, and apparatus for providing polling signals to each of the controllers and circuits on the link bus and for receiving acknowledgement signals therefrom, and thereby synchronizing and allowing exchange of control information between the controllers and circuits.
摘要翻译：计算机系统由主总线和附加的扩展总线，连接到主总线的CPU，连接到主总线或扩展总线之一的外围设备组成，连接到总线的子系统，用于接收控制来自CPU的地址和数据信号，包括图形控制器，数据压缩电路，视频控制器，连接到电路的数据输入端口的存储器和经由具有足以承载视频和图形显示信号的带宽的子系统总线的子系统总线，用于确定哪个控制器被允许访问存储器的第一仲裁器，连接每个控制器的链路总线以及用于向链路总线上的每个控制器和电路提供轮询信号并用于从其接收确认信号的装置，允许在控制器和电路之间交换控制信息。

89. 发明授权

US5293493A Preemption control for central processor with cache 失效
标题翻译：具有缓存的中央处理器抢占控制
公开(公告)号：US5293493A
公开(公告)日：1994-03-08
申请号：US428259
申请日：1989-10-27
申请人： Bruce A. Smith , Loc T. Tran
发明人： Bruce A. Smith , Loc T. Tran
IPC分类号： G06F13/362 , G06F12/08 , G06F13/366 , G06F13/00
CPC分类号： G06F13/366
摘要： A logic controlled gate is inserted in the arbitration logic of a computer system that supports multiple masters on a data bus. In such a system with arbitration for data bus ownership, the gate is so controlled that competitors for the data bus cannot force the main processor (CPU) from the data bus until certain system conditions are met. In particular, a pattern of CPU "hits" to memory cache is recognized as an opportunity for the CPU to relinquish the data bus.
摘要翻译：逻辑控制门被插入到在数据总线上支持多个主器件的计算机系统的仲裁逻辑中。在这种具有数据总线所有权仲裁的系统中，门被如此控制，使得数据总线的竞争对手不能强制主处理器（CPU）从数据总线直到满足某些系统条件。特别地，CPU“命中”到存储器缓存的模式被认为是CPU放弃数据总线的机会。

90. 发明授权

US5269006A Method and apparatus for arbitrating access to a microprocessor having real and protected modes 失效
标题翻译：用于仲裁访问具有真实和受保护模式的微处理器的方法和装置
公开(公告)号：US5269006A
公开(公告)日：1993-12-07
申请号：US866948
申请日：1992-04-08
申请人： William F. Dohse , Ronald J. Larson , Richard Mansfield
发明人： William F. Dohse , Ronald J. Larson , Richard Mansfield
IPC分类号： G06F13/366 , G06F13/32
CPC分类号： G06F13/366
摘要： A microprocessor access arbitration network which arbitrates among HOLD, RESET and REFRESH request commands by controlling a preempt bus so that a system memory refresh cycle is never delayed by a DMA or bus master operation is described. If a HOLD request is in progress for an operation other than a REFRESH cycle when a REFRESH cycle is initiated, that HOLD request is delayed while the REFRESH cycle proceeds to completion.
摘要翻译：描述了通过控制抢占总线在HOLD，RESET和REFRESH请求命令之间进行仲裁的微处理器访问仲裁网络，使得系统存储器刷新周期不会被DMA或总线主机操作延迟。如果在REFRESH周期启动时对于REFRESH周期以外的操作执行了HOLD请求，则在REFRESH周期进行到完成时，该延迟请求被延迟。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式