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81. 发明专利

DE102004024603B4 Verfahren zum Herstellen einer Halbleitereinrichtung mit Oxidfilmschichten verschiedener Stärken 未知
公开(公告)号：DE102004024603B4
公开(公告)日：2010-11-25
申请号：DE102004024603
申请日：2004-05-13
申请人： ELPIDA MEMORY INC
发明人： KANDA TAKAYUKI
IPC分类号： H01L21/336 , H01L21/316 , H01L21/8234 , H01L21/8244 , H01L27/088 , H01L27/10 , H01L27/11

82. 发明专利

DE19928075B4 未知
公开(公告)号：DE19928075B4
公开(公告)日：2010-04-08
申请号：DE19928075
申请日：1999-06-12
申请人： ELPIDA MEMORY INC
发明人： KAWAMURA MASASHI
IPC分类号： H01L23/40 , H01L25/10 , H01L23/34 , H01L23/36 , H01L23/367 , H01L25/18
摘要： A memory module 10 is fitted with a "cover and heat sink" 5 having a U-shape in cross section in such a manner that the memory module 10 is inserted into a U-shaped deep recess of the "cover and heat sink" 5, and all packaged memory ICs 3 and the other components 2 mounted on each face of a printed circuit board 1 are covered by the "cover and heat sink" 5, with a silicone grease 6 being filled between the "cover and heat sink" 5 and the packaged memory ICs 3. The heat generated in each packaged memory IC 3 is conducted to the "cover and heat sink" 5 through the silicone grease 6, and the heat is radiated from the surface of the "cover and heat sink" 5 having a large surface area. In addition, since all the components 2 and 3 mounted on the printed circuit board 1 are covered with the "cover and heat sink" 5, the components 2 and 3 mounted on the printed circuit board 1 are protected from a mechanical shock. Furthermore, it is possible to discriminate whether or not the degree of the warping of the printed circuit board 1 exceeds a permissible limit. Because, if the warping of the printed circuit board exceeds a certain limit, the memory module cannot be inserted into the U-shaped deep recess of the "cover and heat sink" 5.

83. 发明专利

DE10135065B4 未知
公开(公告)号：DE10135065B4
公开(公告)日：2010-01-28
申请号：DE10135065
申请日：2001-07-18
申请人： ELPIDA MEMORY INC
发明人： MOCHIDA YOSHIFUMI
IPC分类号： G11C8/08 , G11C11/407 , G11C7/02 , G11C8/10 , G11C8/14 , G11C11/401 , G11C11/408
摘要： A semiconductor memory device (10) having a peripheral ground line (GND) receiving charge when discharging a sub-word line (SWL) is provided. The semiconductor memory device (10) can include a row decoder (XDEC1), RA driver (RAD11), and sub-decoder blocks (SB). Row decoder (XDEC1) may activate a main word line (MWL) based on a received address value. RA driver (RAD11) may activate a sub-decoder block (SB) from a group of sub-decoder blocks coupled to the activated main word line (MWL). RA driver (RAD11) may provide a current path (4) to peripheral ground (GND) when the sub-word line (SWL) transitions from the activated state to the unactivated state. Non-selected sub-word lines may have a current path (1, 2, or 3) to a word line ground (GNDXDEC) for holding the other word lines at a "quiet" ground potential. Noise produced from discharging a sub-word line may not affect non-selected word lines.

84. 发明专利

DE102008028514A1 未知
公开(公告)号：DE102008028514A1
公开(公告)日：2009-01-08
申请号：DE102008028514
申请日：2008-06-16
申请人： ELPIDA MEMORY INC
发明人： KAJIGAYA KAZUHIKO
IPC分类号： G11C11/4074
摘要： To increase the quantity of stored charges of memory cells by a simple configuration to improve the operating margin, and to allow dummy cells to be unnecessary to improve the operating margin of a DRAM without increasing the power consumption and/or the chip area. A voltage of a common plate line is changed from a first voltage to a second voltage lower than the first voltage while a word line is a third voltage which makes the word line a selected state. The voltage of the word line is changed into a fourth voltage which makes the memory cell a non-selected state and is lower than the third voltage and higher than a fifth voltage which makes the word line a non-selected state, and the voltage of the plate line is changed into the first voltage after the voltage of the word line has been changed into the fourth voltage.

85. 发明专利

DE102008021348A1 未知
公开(公告)号：DE102008021348A1
公开(公告)日：2008-11-27
申请号：DE102008021348
申请日：2008-04-29
申请人： ELPIDA MEMORY INC
发明人： KAJIGAYA KAZUHIKO
IPC分类号： G11C7/22 , G06F13/14 , G06F13/18
摘要： In order to provide a semiconductor memory apparatus which can flexibly change the priority of reading requests when the reading request is issued and which do not exclusively use the memory bus, a semiconductor memory apparatus includes: a main memory which stores data at an address while maintaining a corresponding relationship between the data and the address; a read request input portion receiving a read request which maintains a corresponding relationship between address information that is referred to when reading the data and priority information that indicates priority for reading the data; a read data storing portion which stores the data and priority while maintaining a corresponding relationship thereof; a data reading portion reads the data corresponding to address information which is input by the read request input portion from the main memory; a read data registration portion storing both the priority information input by the read request input and the data read by the data reading portion to the read data storing portion while maintaining a corresponding relationship between the priority information and the data read; and a priority operation control portion which chooses and outputs the data with a highest priority among the priority information and the data that are stored in the read data storing portion while maintaining a corresponding relationship between the priority information and the data.

86. 发明专利

DE10235739B4 未知
公开(公告)号：DE10235739B4
公开(公告)日：2008-08-14
申请号：DE10235739
申请日：2002-07-30
申请人： ELPIDA MEMORY INC
发明人： NISHIO YOJI , FUNABA SEIJI , SHIBATA KAYOKO , SUGANO TOSHIO , IKEDA HIROAKI , IIZUKA TAKUO , SORIMACHI MASAYUKI
IPC分类号： G06F1/04 , G11C11/407 , G06F12/00 , G06F12/06 , G11C7/10 , G11C8/00 , G11C8/06 , G11C11/409
摘要： First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of ½ of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of signals which temporarily has two times. For example, one of the set of signals has only data contents of an odd-th command/address signal, and the other has only data contents of an even-th command/address signal. Since the set of signals has twice periods of the command/address signal, first and second post-processing flip-flop can latch signals in accordance with an internal clock signal generated by a delay locked loop circuit in a state in which a set-up time and a hold time are sufficiently assured.

87. 发明专利

DE102007040577A1 未知
公开(公告)号：DE102007040577A1
公开(公告)日：2008-04-10
申请号：DE102007040577
申请日：2007-08-28
申请人： ELPIDA MEMORY INC
发明人： FUJISAWA HIROKI , TAKISHITA RYUJI
IPC分类号： G11C11/4076 , G06F1/06 , G11C11/407 , H03K5/13
摘要： A DLL circuit includes a first delay adjusting circuit that adjusts an amount of delay of a frequency-divided signal CK1, a second delay adjusting circuit that adjusts an amount of delay of a frequency-divided signal CK2, a synthesizing circuit that synthesizes outputs of these delay adjusting circuits to generate an internal clock signal, and supplies the internal clock signal to a real path, a clock driver that receives the output of the first delay adjusting circuit and supplies the output to a replica path, and a clock driver that receives the output of the second delay adjusting circuit. These clock drivers have substantially the same circuit configuration. Accordingly, even when the power supply voltage fluctuates, influences of the fluctuations on the respective frequency-divided signals are almost equal. Thus, deterioration of the function of the DLL circuit due to fluctuations of the power supply voltage can be prevented.

88. 发明专利

DE102007040380A1 未知
公开(公告)号：DE102007040380A1
公开(公告)日：2008-04-10
申请号：DE102007040380
申请日：2007-08-27
申请人： ELPIDA MEMORY INC
发明人： KINOSHITA HIROTO , FUJISAWA HIROKI
IPC分类号： G11C7/10
摘要： An output circuit of a semiconductor includes unit buffers, each unit buffer having transistors and resistors connected between a power source terminal VDDQ and an output terminal DQ, and transistors and resistors connected between a power source terminal VSSQ and an output terminal DQ. On-resistance values of transistors included in the unit buffers are mutually substantially the same, and resistance values of resistors included in the unit buffers are mutually different. A deviation of impedances attributable to a power source resistance can be offset based on a difference between resistance values of the resistors.

89. 发明专利

DE69936277T2 未知
公开(公告)号：DE69936277T2
公开(公告)日：2007-10-04
申请号：DE69936277
申请日：1999-04-26
申请人： ELPIDA MEMORY INC
发明人： TANIGUCHI JUNYA , KOSHIKAWA YASUJI , MINE KOUJI
IPC分类号： G01R31/28 , G11C29/00 , G01R31/317 , G11C11/401 , G11C11/407 , G11C11/413 , G11C29/14 , G11C29/56
摘要： According to one disclosed embodiment, a synchronous semiconductor storage device (100) includes a circuit for accomplishing mode setting operations after a test mode is entered, where the test mode includes a higher frequency internal clock. A synchronous semiconductor storage device (100) generates a first internal synchronous clock signal ICLK which can be used to enter mode setting values to a mode register setting circuit (122). At the same time, an external synchronous signal CSB can be applied to generate a second internal synchronous clock signal CSCLK. The ICLK and CSCLK values can be used to generate a higher frequency clock ICLK' in a test mode. The ICLK' signal can be applied to internal circuits (124) allowing such circuits to operate at a higher speed. The ICLK' signal is not applied to the mode register setting circuit (122), thereby avoiding the possible latching of incorrect mode setting values by the mode register setting circuit (122).

90. 发明专利

DE102006048846A1 未知
公开(公告)号：DE102006048846A1
公开(公告)日：2007-09-13
申请号：DE102006048846
申请日：2006-10-16
申请人： ELPIDA MEMORY INC
发明人： FUJISAWA HIROKI , YOKO HIDEYUKI
IPC分类号： H04L25/12 , G11C7/10 , G11C11/401 , G11C11/4093 , H03K19/0175

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