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81. 发明授权

US07538382B1 Non-volatile two-transistor programmable logic cell and array layout 有权
公开(公告)号：US07538382B1
公开(公告)日：2009-05-26
申请号：US11927237
申请日：2007-10-29
申请人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , William C. Plants , Zhigang Wang
发明人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , William C. Plants , Zhigang Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/11524 , H01L27/0203 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11526 , H01L27/11529 , H01L29/7881
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

82. 发明授权

US07501681B2 Non-volatile two-transistor programmable logic cell and array layout 有权
公开(公告)号：US07501681B2
公开(公告)日：2009-03-10
申请号：US11962615
申请日：2007-12-21
申请人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , Zhigang Wang
发明人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , Zhigang Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/0203 , H01L21/823493 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

83. 发明授权

US07488657B2 Method and system for forming straight word lines in a flash memory array 有权
标题翻译：用于在闪存阵列中形成直线字线的方法和系统
公开(公告)号：US07488657B2
公开(公告)日：2009-02-10
申请号：US11155707
申请日：2005-06-17
申请人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
发明人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7883 , H01L21/2652 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.
摘要翻译：本发明的实施例公开了一种存储器件，其具有具有促进直线字线的源极触点的闪存单元阵列及其制造方法。阵列由隔离多个存储单元列的多个不相交的浅沟槽隔离（STI）区域组成。在形成隧道氧化物层和第一多晶硅层之后，源极列注入n型掺杂剂。植入的源极柱耦合到耦合到与阵列中的存储器单元相关联的多个源极区域的多个公共源极线。源极触点耦合到植入源极柱，用于提供与多个源极区域的电耦合。源触点与一排漏极触点共线，该排触点耦合到与一行存储器单元相关联的漏极区。与漏极触点排共线的源触点的布置允许直线字线形成。

84. 发明申请

US20080319116A1 Soft and strong elastomeric compositions from semicrystalline-amorphous polyolefin block copolymers 有权
标题翻译：来自半结晶非晶形聚烯烃嵌段共聚物的柔软和强力的弹性体组合物
公开(公告)号：US20080319116A1
公开(公告)日：2008-12-25
申请号：US12080971
申请日：2008-04-08
申请人： Glenn H. Fredrickson , Edward J. Kramer , Zhigang Wang
发明人： Glenn H. Fredrickson , Edward J. Kramer , Zhigang Wang
IPC分类号： C08K3/20 , C08L51/00 , B29C55/30 , B29C55/12 , B29C47/78
CPC分类号： C08J3/075 , B29C47/0014 , B29C47/0016 , B29C47/0021 , B29C47/786 , B29C47/90 , B29C47/906 , C08J2351/06 , C08J2353/00 , C08L51/06 , C08L53/00 , C08L2205/03 , C08L2666/24
摘要： Polyolefin block and graft copolymers comprised of two or more semicrystalline polyolefin blocks or grafts and one or more amorphous polyolefin blocks can be blended with a low molecular weight fluid diluent that preferentially locates within and swells the amorphous domains of the block or graft copolymer, while preserving the crystallinity of the semicrystalline block domains. After mechanical or thermomechanical processing, such compositions combine softness with high strength and high recoverable elasticity. Compositions are also disclosed whereby the diluent species is removed from the composition, either before or after the mechanical or thermomechanical processing, in order to create a strong elastic material with an ultra-low entanglement density within the amorphous domains.
摘要翻译：由两个或更多个半结晶聚烯烃嵌段或接枝物和一个或多个非晶形聚烯烃嵌段组成的聚烯烃嵌段和接枝共聚物可以与低分子量流体稀释剂共混，该低分子量流体稀释剂优选位于嵌段或接枝共聚物的无定形区域内并溶胀，同时保留半结晶区域的结晶度。在机械或热机械加工之后，这种组合物将柔软度与高强度和高可恢复弹性相结合。还公开了组合物，其中在机械或热机械加工之前或之后从组合物中除去稀释剂物质，以便在无定形区域内产生具有超低缠结密度的强弹性材料。

85. 发明申请

US20080276143A1 Method and apparatus for broadcasting scan patterns in a random access based integrated circuit 有权
标题翻译：用于在基于随机接入的集成电路中广播扫描模式的方法和装置
公开(公告)号：US20080276143A1
公开(公告)日：2008-11-06
申请号：US12216640
申请日：2008-07-09
申请人： Laung-Terng (L.-T.) Wang , Boryau (Jack) Sheu , Zhigang Jiang , Zhigang Wang , Shianling Wu
发明人： Laung-Terng (L.-T.) Wang , Boryau (Jack) Sheu , Zhigang Jiang , Zhigang Wang , Shianling Wu
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547 , G01R31/318533 , G01R31/318591 , G01R31/31926
摘要： A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.The scan architecture used can also be random access scan based, where the integrated circuit comprises an array of random access scan (RAS) cells that are randomly and uniquely addressable. In random access scan, test patterns can be applied by selectively updating RAS cells and test responses can be observed through a direct read-out process. Eliminating the shifting process inherent in serial scan, random access scan produces much lower test power dissipation than serial scan.
摘要翻译：用于在基于扫描的集成电路中的ATE（自动测试设备）中降低测试数据量和测试应用时间的广播，系统和方法。基于扫描的集成电路包含多个扫描链，每个扫描链包括串联耦合的多个扫描单元。广播公司是组合逻辑网络，耦合到可选的虚拟扫描控制器和可选的扫描连接器。虚拟扫描控制器控制广播机构的操作。系统发送存储在ATE中的虚拟扫描模式，并通过广播机构生成广播扫描模式，以测试基于扫描的集成电路中的制造故障。 ATE可以支持的扫描链数显着增加。进一步提出了方法来重新排列所选择的扫描链中的扫描单元，以产生广播扫描图案和虚拟扫描图案，并且在基于扫描的集成电路中合成广播器和压缩器。所使用的扫描结构也可以是基于随机存取扫描的集成电路，其中集成电路包括随机访问扫描（RAS）阵列，其随机且唯一可寻址。在随机存取扫描中，可以通过选择性地更新RAS细胞来应用测试模式，并且可以通过直接读出过程来观察测试响应。消除串行扫描固有的移位过程，随机访问扫描产生比串行扫描低得多的测试功耗。

86. 发明授权

US07412637B2 Method and apparatus for broadcasting test patterns in a scan based integrated circuit 有权
标题翻译：用于在基于扫描的集成电路中广播测试模式的方法和装置
公开(公告)号：US07412637B2
公开(公告)日：2008-08-12
申请号：US11348519
申请日：2006-02-07
申请人： Laung-Terng (L.-T.) Wang , Boryau (Jack) Sheu , Zhigang Jiang , Zhigang Wang , Shianling Wu
发明人： Laung-Terng (L.-T.) Wang , Boryau (Jack) Sheu , Zhigang Jiang , Zhigang Wang , Shianling Wu
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/318533 , G01R31/318591 , G01R31/31926
摘要： A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.The scan architecture used can also be random access scan based, where the integrated circuit comprises an array of random access scan (RAS) cells that are randomly and uniquely addressable. In random access scan, test patterns can be applied by selectively updating RAS cells and test responses can be observed through a direct read-out process. Eliminating the shifting process inherent in serial scan, random access scan produces much lower test power dissipation than serial scan.
摘要翻译：用于在基于扫描的集成电路中的ATE（自动测试设备）中降低测试数据量和测试应用时间的广播，系统和方法。基于扫描的集成电路包含多个扫描链，每个扫描链包括串联耦合的多个扫描单元。广播公司是组合逻辑网络，耦合到可选的虚拟扫描控制器和可选的扫描连接器。虚拟扫描控制器控制广播机构的操作。系统发送存储在ATE中的虚拟扫描模式，并通过广播机构生成广播扫描模式，以测试基于扫描的集成电路中的制造故障。 ATE可以支持的扫描链数显着增加。进一步提出了方法来重新排列所选择的扫描链中的扫描单元，以产生广播扫描图案和虚拟扫描图案，并且在基于扫描的集成电路中合成广播器和压缩器。所使用的扫描结构也可以是基于随机存取扫描的集成电路，其中集成电路包括随机访问扫描（RAS）阵列，其随机且唯一可寻址。在随机存取扫描中，可以通过选择性地更新RAS细胞来应用测试模式，并且可以通过直接读出过程来观察测试响应。消除串行扫描固有的移位过程，随机访问扫描产生比串行扫描低得多的测试功耗。

87. 发明授权

US07342278B2 Non-volatile two-transistor programmable logic cell and array layout 失效
标题翻译：非易失性双晶体管可编程逻辑单元和阵列布局
公开(公告)号：US07342278B2
公开(公告)日：2008-03-11
申请号：US11750650
申请日：2007-05-18
申请人： Fethi Dhaoui , John McCollum , Vidyahara Bellippady , Zhigang Wang
发明人： Fethi Dhaoui , John McCollum , Vidyahara Bellippady , Zhigang Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/0203 , H01L21/823493 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
摘要翻译：在半导体本体中形成双晶体管非易失性存储单元。记忆晶体管阱设置在半导体本体内。开关晶体管阱设置在半导体本体内并与存储晶体管良好地电隔离。包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。

88. 发明授权

US07289639B2 Hearing implant 有权
标题翻译：听力植入
公开(公告)号：US07289639B2
公开(公告)日：2007-10-30
申请号：US10502367
申请日：2003-01-24
申请人： Eric Abel , Zhigang Wang , Robert Mills
发明人： Eric Abel , Zhigang Wang , Robert Mills
IPC分类号： H04R25/00
CPC分类号： H04R25/606 , H04R23/008 , H04R2225/023 , H04R2225/67
摘要： The present invention relates to a hearing aid system comprising a hearing implant and a method of powering a hearing implant, the system comprising an external ear canal module and an implant, wherein the signalling and/or powering of the ear implant is by way of a light signal being provided to the implant through the ear drum from, for example, the ear canal module.
摘要翻译：本发明涉及一种助听器系统，其包括听力植入物和为听力植入物提供动力的方法，所述系统包括外耳道模块和植入物，其中所述耳朵植入物的信号和/或动力通过光信号通过耳鼓从例如耳道模块提供给植入物。

89. 发明授权

US07285818B2 Non-volatile two-transistor programmable logic cell and array layout 有权
标题翻译：非易失性双晶体管可编程逻辑单元和阵列布局
公开(公告)号：US07285818B2
公开(公告)日：2007-10-23
申请号：US11155005
申请日：2005-06-15
申请人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , Zhigang Wang
发明人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , Zhigang Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/0203 , H01L21/823493 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
摘要翻译：在半导体本体中形成双晶体管非易失性存储单元。记忆晶体管阱设置在半导体本体内。开关晶体管阱设置在半导体本体内并与存储晶体管良好地电隔离。包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。

90. 发明授权

US07170130B2 Memory cell with reduced DIBL and Vss resistance 有权
标题翻译：具有降低的DIBL和Vss电阻的存储单元
公开(公告)号：US07170130B2
公开(公告)日：2007-01-30
申请号：US10915771
申请日：2004-08-11
申请人： Shenqing Fang , Kuo-Tung Chang , Pavel Fastenko , Zhigang Wang
发明人： Shenqing Fang , Kuo-Tung Chang , Pavel Fastenko , Zhigang Wang
IPC分类号： H01L29/788
CPC分类号： H01L29/66825
摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory cell on substrate comprises a step of forming a spacer adjacent to a source sidewall of a stacked gate structure, where the stacked gate structure is situated over a channel region in substrate. The method further comprises forming a high energy implant doped region adjacent to the spacer in the source region of substrate. The method further comprises forming a recess in a source region of the substrate, where the recess has a sidewall, a bottom, and a depth, and where the sidewall of the recess is situated adjacent to a source of the floating gate memory cell. According to this exemplary embodiment, the spacer causes the source to have a reduced lateral straggle and diffusion in the channel region, which causes a reduction in drain induced barrier lowering (DIBL) in the floating gate memory cell.
摘要翻译：根据一个示例性实施例，用于在衬底上制造浮动栅极存储器单元的方法包括形成与层叠栅极结构的源极侧壁相邻的间隔物的步骤，其中堆叠的栅极结构位于衬底中的沟道区域之上。该方法还包括在衬底的源区中形成与间隔物相邻的高能注入掺杂区。该方法还包括在衬底的源极区域中形成凹部，其中凹部具有侧壁，底部和深度，并且凹部的侧壁位于与浮动栅极存储单元的源极相邻的位置。根据该示例性实施例，间隔件导致源极在通道区域中具有减小的横向偏移和扩散，这导致浮动栅极存储单元中的漏极感应势垒降低（DIBL）的减小。

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