专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明申请

US20130224931A1 NONVOLATILE MEMORY DEVICE MANUFACTURING METHOD 有权
标题翻译：非易失性存储器件制造方法
公开(公告)号：US20130224931A1
公开(公告)日：2013-08-29
申请号：US13884630
申请日：2012-03-21
申请人： Haruyuki Sorada , Takumi Mikawa , Kenji Tominaga , Kiyotaka Tsuji
发明人： Haruyuki Sorada , Takumi Mikawa , Kenji Tominaga , Kiyotaka Tsuji
IPC分类号： H01L45/00
CPC分类号： H01L45/16 , H01L27/101 , H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L45/04 , H01L45/1683
摘要： A method of manufacturing a nonvolatile memory device that is a variable resistance nonvolatile memory device, which has good consistency with a dual damascene process that is suitable for the formation of fine copper lines and which enables large capacity and high integration. This method includes: forming a variable resistance element, a contact hole and a line groove; and forming a current steering layer of a bidirectional diode element above interlayer insulating layers and a variable resistance layer to cover the line groove without covering a bottom surface of the contact hole.
摘要翻译：一种制造非易失性存储器件的方法，其是可变电阻非易失性存储器件，其与适合于形成细铜线的双镶嵌工艺具有良好的一致性，并且能够实现大容量和高集成度。该方法包括：形成可变电阻元件，接触孔和线槽; 并且在层间绝缘层之上形成双向二极管元件的电流转向层和可变电阻层以覆盖线槽而不覆盖接触孔的底表面。

82. 发明授权

US08482958B2 Current steering element, memory element, memory, and method of manufacturing current steering element 有权
标题翻译：当前的导向元件，存储元件，存储器以及制造电流转向元件的方法
公开(公告)号：US08482958B2
公开(公告)日：2013-07-09
申请号：US13321018
申请日：2011-03-10
申请人： Yukio Hayakawa , Koji Arita , Takumi Mikawa , Takeki Ninomiya
发明人： Yukio Hayakawa , Koji Arita , Takumi Mikawa , Takeki Ninomiya
IPC分类号： G11C11/00
CPC分类号： H01L27/2409 , H01L45/146
摘要： Provided is a current steering element that can prevent write didturb even when an electrical pulse with different polarities is applied and that can cause a large current to flow through a variable resistance element. The current steering element includes a first electrode (32), a second electrode (31), and a current steering layer (33). The current steering layer (33) comprises SiNx (where 0
摘要翻译：提供了即使当施加具有不同极性的电脉冲并且可能导致大电流流过可变电阻元件时也能够防止写入干扰的电流导向元件。当前的转向元件包括第一电极（32），第二电极（31）和电流转向层（33）。当前的转向层（33）包括加入氢或氟的SiNx（其中0 <0.85）。当D（D = D0×1022原子/ cm3）表示氢或氟的密度时，d（nm）表示电流导向层（33）的厚度，V0（V）表示适用于第一电极（32）和第二电极（31）D，x，d和V0满足下式。（ln（1000（C·exp（α·d）exp（β·x））-1）γ）2 @ V0 ）γ）2-（ln（10000（C·exp（α·d）exp（β·x））-1）γ）2/2> = 0其中C = k1×D0k2，α，β， k1和k2是常数。

83. 发明授权

US08355274B2 Current steering element, storage element, storage device, and method for manufacturing current steering element 有权
标题翻译：目前的导向元件，存储元件，存储装置以及用于制造当前转向元件的方法
公开(公告)号：US08355274B2
公开(公告)日：2013-01-15
申请号：US13061312
申请日：2009-09-17
申请人： Koji Arita , Takumi Mikawa , Mitsuteru IIjima , Kenji Tominaga
发明人： Koji Arita , Takumi Mikawa , Mitsuteru IIjima , Kenji Tominaga
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2013/0078 , G11C2213/15 , G11C2213/51 , G11C2213/56 , G11C2213/76 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1625
摘要： A current steering element which can prevent occurrence of write disturb even when electric pulses having different polarities are applied and can cause large current to flow through a variable resistance element, and with which data can be written without problem. In a storage element (3) including: a variable resistance element (1) whose electric resistance value changes in response to application of electric pulses having a positive polarity and a negative polarity and which maintains the changed electric resistance value; and the current steering element (2) that steers current flowing through the variable resistance element (1) when the electric pulses are applied, the current steering element (2) includes: a first electrode (32); a second electrode (31); and a current steering layer (33) interposed between the first electrode (32) and the second electrode (31). When the current steering layer (33) includes SiNx (0
摘要翻译：即使施加具有不同极性的电脉冲也能够防止写入干扰的发生，并且可能导致大的电流流过可变电阻元件并且可以无限制地写入数据的电流导向元件。在一种存储元件（3）中，包括：可变电阻元件（1），其电阻值响应于具有正极性和负极性的电脉冲的应用而变化并且保持改变的电阻值; 以及当施加电脉冲时转向流过可变电阻元件（1）的电流的当前操舵元件（2），所述电流操舵元件（2）包括：第一电极（32）; 第二电极（31）; 和介于所述第一电极（32）和所述第二电极（31）之间的电流转向层（33）。当电流导向层（33）包括SiNx（0

84. 发明申请

US20130010529A1 NONVOLATILE MEMORY ELEMENT, MANUFACTURING METHOD THEREOF, NONVOLATILE MEMORY DEVICE, AND DESIGN SUPPORT METHOD FOR NONVOLATILE MEMORY ELEMENT 有权
标题翻译：非易失性存储器元件，其制造方法，非易失性存储器件以及非易失性存储元件的设计支持方法
公开(公告)号：US20130010529A1
公开(公告)日：2013-01-10
申请号：US13634700
申请日：2011-11-24
申请人： Yukio Hayakawa , Takumi Mikawa , Takeki Ninomiya
发明人： Yukio Hayakawa , Takumi Mikawa , Takeki Ninomiya
IPC分类号： H01L45/00 , G11C11/00 , G06F17/50
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/32 , G11C2213/34 , G11C2213/55 , H01L27/02 , H01L27/2427 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A nonvolatile memory element includes a variable resistance layer located between a lower electrode and an upper electrode and having a resistance value that reversibly changes based on electrical signals applied between these electrodes. The variable resistance layer includes at least two layers: a first variable resistance layer including a first transition metal oxide; and a second variable resistance layer including a second transition metal oxide and a transition metal compound. The second transition metal oxide has an oxygen content atomic percentage lower than an oxygen content atomic percentage of the first transition metal oxide, the transition metal compound contains either oxygen and nitrogen or oxygen and fluorine, and the second transition metal oxide and the transition metal compound are in contact with the first variable resistance layer.
摘要翻译：非易失性存储元件包括位于下电极和上电极之间的可变电阻层，并且具有基于施加在这些电极之间的电信号而可逆地改变的电阻值。可变电阻层包括至少两层：包含第一过渡金属氧化物的第一可变电阻层; 以及包含第二过渡金属氧化物和过渡金属化合物的第二可变电阻层。第二过渡金属氧化物的氧含量原子百分比低于第一过渡金属氧化物的氧含量原子百分比，过渡金属化合物含有氧和氮或氧和氟，第二过渡金属氧化物和过渡金属化合物与第一可变电阻层接触。

85. 发明申请

US20130001504A1 NONVOLATILE MEMORY ELEMENT AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：非易失性存储元件及其制造方法
公开(公告)号：US20130001504A1
公开(公告)日：2013-01-03
申请号：US13501624
申请日：2011-11-18
申请人： Takeki Ninomiya , Takumi Mikawa , Yukio Hayakawa
发明人： Takeki Ninomiya , Takumi Mikawa , Yukio Hayakawa
IPC分类号： H01L45/00
CPC分类号： H01L45/146 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/1675
摘要： Provided is a nonvolatile memory element which inhibits deterioration of a oxygen concentration profile of a variable resistance layer due to a thermal budget and is able to stably operate at low voltages, and a method for manufacturing the nonvolatile memory element. A nonvolatile memory element (12) includes a first electrode layer (105) formed above a substrate (100), a variable resistance layer (106) disposed on the first electrode layer (105), and a second electrode layer (107) disposed on the variable resistance layer (106), and the variable resistance layer (106) has a two-layer structure in which a oxygen- and/or nitrogen-deficient tantalum oxynitride layer (106a) and a tantalum oxide layer (106b) are stacked.
摘要翻译：提供一种非易失性存储元件，其抑制由于热量预算而导致的可变电阻层的氧浓度分布的劣化，并能够稳定地在低电压下工作，以及非易失性存储元件的制造方法。非易失性存储元件（12）包括形成在基板（100）上方的第一电极层（105），设置在第一电极层（105）上的可变电阻层（106）和设置在第一电极层可变电阻层（106）和可变电阻层（106）具有堆叠氧和/或氮缺乏的氮氧化钽层（106a）和氧化钽层（106b）的双层结构。

86. 发明申请

US20120292588A1 NONVOLATILE MEMORY DEVICE 审中-公开
标题翻译：非易失性存储器件
公开(公告)号：US20120292588A1
公开(公告)日：2012-11-22
申请号：US13503770
申请日：2011-12-15
申请人： Satoru Fujii , Haruyuki Sorada , Takumi Mikawa
发明人： Satoru Fujii , Haruyuki Sorada , Takumi Mikawa
IPC分类号： H01L47/00
CPC分类号： H01L45/145 , H01L27/2418 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1616 , H01L45/1625 , H01L45/1683
摘要： A nonvolatile memory device including: a strip-shaped first electrode line (151); a third interlayer insulating layer (16); a variable resistance layer having a stacked structure including a first variable resistance layer (18a) comprising an oxygen-deficient transition metal oxide and formed in a memory cell hole (29) to cover a bottom and a side face, and a second variable resistance layer (18b) comprising an oxygen- and/or nitrogen-deficient transition metal oxynitride having a different oxygen content than the first variable resistance layer; a first electrode (19) formed in the memory cell hole; and a strip-shaped first line (22) formed in a direction crossing the first electrode line (151) to cover at least an opening of the memory cell hole, and z>(x+y) is satisfied when the transition metal is represented by M and compositions of the first and the second variable resistance layers by MOz and MOxNy, respectively.
摘要翻译：一种非易失性存储器件，包括：带状第一电极线（151）; 第三层间绝缘层（16）; 具有堆叠结构的可变电阻层，包括由缺氧过渡金属氧化物构成的第一可变电阻层（18a），形成在存储单元孔（29）中以覆盖底部和侧面;以及第二可变电阻层（18b），其包含氧含量低于所述第一可变电阻层的氧和/或氮缺乏的过渡金属氮氧化物; 形成在所述存储单元孔中的第一电极（19）以及沿着与第一电极线（151）交叉的方向形成的带状第一线（22），以覆盖存储单元孔的至少一个开口，并且当表示过渡金属时，满足z>（x + y）分别由M和第一和第二可变电阻层的组成分别由MOz和MOxNy组成。

87. 发明授权

US08295123B2 Current rectifying element, memory device incorporating current rectifying element, and fabrication method thereof 有权
标题翻译：电流整流元件，并联电流整流元件的存储器件及其制造方法
公开(公告)号：US08295123B2
公开(公告)日：2012-10-23
申请号：US12669174
申请日：2008-07-11
申请人： Takeshi Takagi , Takumi Mikawa , Koji Arita , Mitsuteru Iijima , Takashi Okada
发明人： Takeshi Takagi , Takumi Mikawa , Koji Arita , Mitsuteru Iijima , Takashi Okada
IPC分类号： G11C13/00
CPC分类号： H01L27/101 , H01L27/1021 , H01L27/24 , H01L45/00
摘要： In a current rectifying element (10), a barrier height φA of a center region (14) of a barrier layer (11) in a thickness direction thereof sandwiched between a first electrode layer (12) and a second electrode layer (13) is formed to be larger than a barrier height φB of a region in the vicinity of an interface (17) between the barrier layer (11) and the first electrode layer (12) and an interface (17) between the barrier layer (11) and the second electrode layer (13). The barrier layer (11) has, for example, a triple-layer structure of barrier layers (11a), (11b) and (11c). The barrier layers (11a), (11b) and (11c) are, for example, formed by SiN layers of SiNx2, SiNx1, and SiNx1 (X1
摘要翻译：在电流整流元件（10）中，阻挡层（11）在其厚度方向上的中心区域（14）的阻挡高度＆amp; A被夹在第一电极层（12）和第二电极层（13）之间）形成为大于阻挡层（11）和第一电极层（12）之间的界面（17）附近的区域和阻挡层（17）之间的界面（17）的势垒高度B （11）和第二电极层（13）。阻挡层（11）具有例如阻挡层（11a），（11b）和（11c）的三层结构。阻挡层（11a），（11b）和（11c）例如由SiNx2，SiNx1和SiNx1（X1

88. 发明申请

US20120256156A1 MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20120256156A1
公开(公告)日：2012-10-11
申请号：US13515592
申请日：2010-11-17
申请人： Koji Arita , Takumi Mikawa
发明人： Koji Arita , Takumi Mikawa
IPC分类号： H01L47/00 , H01L21/02
CPC分类号： G11C13/0007 , G11C2213/79 , H01L27/101 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： Disclosed is a memory device provided with a plurality of memory cells and a lead-out line (12) shared among the memory cells. Each memory cell is provided with a transistor (6) formed above a substrate (1) and a variable resistance element (10) having a lower electrode (7), an upper electrode (9) that comprises a noble metal, and a variable resistance layer (8) disposed between the lower electrode (7) and the upper electrode (9). The resistance value of the variable resistance layer (8) changes reversibly in response to electric pulses that go through the transistor (6) and are applied between the lower electrode (7) and the upper electrode (9). The lead-out line (12) is in direct contact with the upper electrodes (9) of the memory cells.
摘要翻译：公开了一种设置有多个存储单元和在存储单元之间共享的引出线（12）的存储器件。每个存储单元设置有形成在基板（1）上方的晶体管（6）和具有下电极（7）的可变电阻元件（10），包含贵金属的上电极（9）和可变电阻层（8）设置在下电极（7）和上电极（9）之间。可变电阻层（8）的电阻值响应于通过晶体管（6）的电脉冲而可逆地改变并施加在下电极（7）和上电极（9）之间。引出线（12）与存储单元的上电极（9）直接接触。

89. 发明申请

US20120161095A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120161095A1
公开(公告)日：2012-06-28
申请号：US13392555
申请日：2010-08-26
申请人： Takumi Mikawa , Takashi Okada
发明人： Takumi Mikawa , Takashi Okada
IPC分类号： H01L47/00 , H01L21/02
CPC分类号： H01L45/1608 , H01L27/101 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/1675
摘要： Provided are a variable resistance semiconductor memory device which changes its resistance without being affected by an underlying layer and is suitable as a memory device of increased capacity, and a method of manufacturing the same. The semiconductor memory device in the present invention includes: a first contact plug (104) formed inside a first contact hole (103) penetrating through a first interlayer insulating layer (102); a lower electrode (105) having a flat top surface and is thicker above the first interlayer insulating layer (102) than above the first contact plug (104); a variable resistance layer (106); and an upper electrode (107). The lower electrode (105), the variable resistance layer (106), and the upper electrode (107) compose a variable resistance element.
摘要翻译：提供一种可变电阻半导体存储器件，其改变其电阻而不受下层影响，并且适合作为增加容量的存储器件及其制造方法。本发明的半导体存储器件包括：形成在穿过第一层间绝缘层（102）的第一接触孔（103）内的第一接触插塞（104）; 具有平坦顶表面并且比第一接触插头（104）上方更厚于第一层间绝缘层（102）上方的下电极（105）; 可变电阻层（106）; 和上电极（107）。下电极（105），可变电阻层（106）和上电极（107）构成可变电阻元件。

90. 发明授权

US07915656B2 Nonvolatile semiconductor memory apparatus and manufacturing method thereof 有权
标题翻译：非易失性半导体存储装置及其制造方法
公开(公告)号：US07915656B2
公开(公告)日：2011-03-29
申请号：US12446964
申请日：2007-10-22
申请人： Takumi Mikawa , Takeshi Takagi
发明人： Takumi Mikawa , Takeshi Takagi
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119 , H01L21/20
CPC分类号： H01L27/101 , H01L27/24
摘要： A nonvolatile semiconductor memory apparatus (10) of the present invention comprises a semiconductor substrate (11), an active element forming region provided on the semiconductor substrate (11) and including a plurality of active elements (12), a wire forming region which is provided on the active element forming region to electrically connect the active elements (12) and includes plural layers of semiconductor electrode wires (15, 16), a memory portion forming region (100) which is provided above the wire forming region and provided with memory portions (26) arranged in matrix, a resistance value of each of the memory portions changing according to electric pulses applied, and an oxygen barrier layer (17) which is provided between the memory portion forming region (100) and the wire forming region so as to extend continuously over at least an entire of the memory portion forming region (100).
摘要翻译：本发明的非易失性半导体存储器件（10）包括半导体衬底（11），设置在半导体衬底（11）上并包括多个有源元件（12）的有源元件形成区域，设置在有源元件形成区域上以电连接有源元件（12）并且包括多层半导体电极线（15,16），存储部形成区域（100），其设置在线形成区域的上方并设置有存储器布置成矩阵的部分（26），每个存储部分的电阻值根据施加的电脉冲而变化，以及设置在存储部分形成区域（100）和线形成区域之间的氧阻挡层（17），从而以在至少整个存储部分形成区域（100）上连续地延伸。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式