专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明申请

US20090242031A1 Photovoltaic Assembly Including a Conductive Layer Between a Semiconductor Lamina and a Receiver Element 审中-公开
标题翻译：包括半导体衬底和接收器元件之间的导电层的光伏组件
公开(公告)号：US20090242031A1
公开(公告)日：2009-10-01
申请号：US12057274
申请日：2008-03-27
申请人： S. Brad Herner , Aditya Agarwal
发明人： S. Brad Herner , Aditya Agarwal
IPC分类号： H01L31/028 , H01L31/04 , H01L21/18
CPC分类号： H01L31/068 , H01L31/075 , H01L31/1896 , Y02E10/547 , Y02E10/548
摘要： A semiconductor donor body is affixed to a receiver element, and a thin semiconductor lamina is cleaved from the donor body, remaining affixed to the receiver element. A photovoltaic assembly is fabricated which includes the lamina and the receiver element, wherein a photovoltaic cell comprises the lamina. The bond between the semiconductor donor body and the receiver element must survive processing to complete the cell, as well as eventual assembly, transport, and operation in a finished photovoltaic module. It has been found that inclusion of a conductive layer such as titanium or aluminum aids bonding between the semiconductor donor body and the receiver element. In some embodiments, the conductive layer may also serve as an electrical contact and/or as a reflective layer.
摘要翻译：将半导体施主体固定到接收器元件，并且将薄的半导体层从施主体断开，保持固定在接收器元件上。制造包括层板和接收器元件的光伏组件，其中光伏电池包括层板。半导体施主体和接收元件之间的结合必须能够经受处理以完成电池，以及在成品光伏模块中的最终组装，运输和操作。已经发现，诸如钛或铝的导电层的包含有助于在半导体施主体和接收体之间粘合。在一些实施例中，导电层还可以用作电接触和/或作为反射层。

82. 发明申请

US20090194162A1 METHOD TO FORM A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA 失效
公开(公告)号：US20090194162A1
公开(公告)日：2009-08-06
申请号：US12026530
申请日：2008-02-05
申请人： Srinivasan Sivaram , Aditya Agarwal , S. Brad Herner , Christopher J. Petti
发明人： Srinivasan Sivaram , Aditya Agarwal , S. Brad Herner , Christopher J. Petti
IPC分类号： H01L31/028 , H01L21/00 , H01L31/04
CPC分类号： H01L31/022425 , H01L31/0682 , H01L31/0747 , H01L31/1804 , H01L31/1892 , Y02E10/547 , Y02P70/521
摘要： A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only.

83. 发明申请

US20090181515A1 Selective germanium deposition for pillar devices 有权
标题翻译：支柱装置的选择性锗沉积
公开(公告)号：US20090181515A1
公开(公告)日：2009-07-16
申请号：US12007780
申请日：2008-01-15
申请人： S. Brad Herner , Christopher J. Petti
发明人： S. Brad Herner , Christopher J. Petti
IPC分类号： H01L21/329
CPC分类号： H01L29/868 , H01L27/1021
摘要： A method of making a pillar device includes providing an insulating layer having an opening, and selectively depositing germanium or germanium rich silicon germanium semiconductor material into the opening to form the pillar device.
摘要翻译：制造柱装置的方法包括提供具有开口的绝缘层，并且将锗或富锗硅锗半导体材料选择性地沉积到开口中以形成柱装置。

84. 发明授权

US07560339B2 Nonvolatile memory cell comprising a reduced height vertical diode 有权
标题翻译：非易失性存储单元包括减小的高度的垂直二极管
公开(公告)号：US07560339B2
公开(公告)日：2009-07-14
申请号：US11866403
申请日：2007-10-02
申请人： S. Brad Herner , Steven J. Radigan
发明人： S. Brad Herner , Steven J. Radigan
IPC分类号： H01L29/80
CPC分类号： G11C5/02 , G11C11/39 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L27/1021 , H01L29/0649 , H01L29/66272 , H01L29/732 , H01L29/868
摘要： A nonvolatile memory cell according to the present invention comprises a bottom conductor, a semiconductor pillar, and a top conductor. The semiconductor pillar comprises a junction diode, including a bottom heavily doped region, a middle intrinsic or lightly doped region, and a top heavily doped region, wherein the conductivity types of the top and bottom heavily doped region are opposite. The junction diode is vertically oriented and is of reduced height, between about 500 angstroms and about 3500 angstroms. A monolithic three dimensional memory array of such cells can be formed comprising multiple memory levels, the levels monolithically formed above one another.
摘要翻译：根据本发明的非易失性存储单元包括底部导体，半导体柱和顶部导体。半导体柱包括结二极管，其包括底部重掺杂区域，中间固有或轻掺杂区域和顶部重掺杂区域，其中顶部和底部重掺杂区域的导电类型相反。结二极管是垂直取向的，并且具有降低的高度，在约500埃至约3500埃之间。可以形成这样的单元的单片三维存储器阵列，其包括多个存储器级，电平彼此整体地形成。

85. 发明申请

US20090085154A1 VERTICAL DIODE BASED MEMORY CELLS HAVING A LOWERED PROGRAMMING VOLTAGE AND METHODS OF FORMING THE SAME 有权
标题翻译：具有降低的编程电压的基于垂直二极管的存储器电池及其形成方法
公开(公告)号：US20090085154A1
公开(公告)日：2009-04-02
申请号：US11864848
申请日：2007-09-28
申请人： S. Brad Herner , Tanmay Kumar
发明人： S. Brad Herner , Tanmay Kumar
IPC分类号： H01L27/102 , H01L21/8229
CPC分类号： H01L27/1021 , G11C17/16 , H01L23/5252 , H01L29/868 , H01L2924/0002 , H01L2924/00
摘要： In a first aspect, a method for forming a non-volatile memory cell is provided. The method includes (1) forming a metal-insulator-metal (MIM) antifuse stack including (a) a first metal layer; (b) a silicon dioxide, oxynitride or silicon nitride antifuse layer formed above the first metal layer; and (c) a second metal layer formed above the antifuse layer. The method also includes (2) forming a contiguous p-i-n diode above the MIM stack, the contiguous p-i-n diode comprising deposited semiconductor material; (3) forming a layer of a silicide, silicide-germanide, or germanide in contact with the deposited semiconductor material; and (4) crystallizing the deposited semiconductor material in contact with the layer of silicide, silicide-germanide, or germanide. The memory cell comprises the contiguous p-i-n diode and the MIM stack. Other aspects are provided.
摘要翻译：在第一方面，提供了一种用于形成非易失性存储单元的方法。该方法包括（1）形成包括（a）第一金属层的金属 - 绝缘体 - 金属（MIM）反熔丝堆叠; （b）形成在第一金属层上方的二氧化硅，氧氮化物或氮化硅反熔层; 和（c）形成在反熔丝层之上的第二金属层。该方法还包括（2）在MIM堆叠之上形成连续的p-i-n二极管，连续的p-i-n二极管包括沉积的半导体材料; （3）形成与沉积的半导体材料接触的硅化物层，硅化锗 - 锗化物或锗化物层; 和（4）使沉积的半导体材料与硅化物，硅化锗 - 锗化物或锗化物层接触。存储单元包括相邻的p-i-n二极管和MIM堆叠。提供其他方面。

86. 发明申请

US20080318397A1 Junction Diode with Reduced Reverse Current 有权
标题翻译：具有降低反向电流的结二极管
公开(公告)号：US20080318397A1
公开(公告)日：2008-12-25
申请号：US11765254
申请日：2007-06-19
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L21/20
CPC分类号： H01L29/861 , G11C17/16 , G11C17/165 , G11C2213/33 , G11C2213/71 , G11C2213/72 , H01L21/02381 , H01L21/02532 , H01L21/02667 , H01L27/1021 , H01L29/161 , H01L29/66136
摘要： A method for annealing a diode formed of a silicon-germanium alloy that minimizes leakage current is disclosed. The method includes the steps of forming semiconductor pillars of an alloy of silicon and germanium; heating the pillars at a first temperature for at least 30 minutes, and then heating the pillars at a second temperature higher than the first temperature of the alloy for up to 120 seconds. The invention further includes a monolithic three dimensional memory array of a plurality of p-i-n diodes, the p-i-n diodes being formed of a silicon-germanium alloy that have been subjected to a two-stage heating process.
摘要翻译：公开了一种使由硅 - 锗合金形成的二极管退火的方法，其使泄漏电流最小化。该方法包括形成硅和锗的合金的半导体柱的步骤; 在第一温度下加热柱子至少30分钟，然后在高于合金的第一温度的第二温度下加热柱子长达120秒。本发明还包括多个p-i-n二极管的单片三维存储器阵列，p-i-n二极管由已进行两级加热处理的硅 - 锗合金形成。

87. 发明申请

US20080316809A1 High forward current diodes for reverse write 3D cell 有权
标题翻译：用于反向写入3D电池的高正向电流二极管
公开(公告)号：US20080316809A1
公开(公告)日：2008-12-25
申请号：US11819078
申请日：2007-06-25
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： G11C11/36
CPC分类号： H01L27/1021 , G11C11/5692 , G11C13/003 , G11C13/0069 , G11C17/16 , G11C17/165 , G11C2013/009 , G11C2213/33 , G11C2213/71 , G11C2213/72 , H01L27/101
摘要： A nonvolatile memory device includes at least one memory cell which comprises a diode and a metal oxide antifuse dielectric layer, and a first electrode and a second electrode electrically contacting the at least one memory cell. In use, the diode acts as a read/write element of the memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.
摘要翻译：非易失性存储器件包括至少一个存储单元，其包括二极管和金属氧化物反熔丝电介质层，以及第一电极和与该至少一个存储单元电接触的第二电极。在使用中，响应于施加的偏压，二极管通过从第一电阻率状态切换到不同于第一电阻率状态的第二电阻率状态来充当存储单元的读/写元件。

88. 发明申请

US20080316796A1 Method of making high forward current diodes for reverse write 3D cell 有权
标题翻译：制造反向写入3D电池的高正向电流二极管的方法
公开(公告)号：US20080316796A1
公开(公告)日：2008-12-25
申请号：US11819079
申请日：2007-06-25
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： G11C11/00 , G11C11/36 , H01L21/82
CPC分类号： G11C11/36 , H01L27/1021
摘要： A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell including a diode and a metal oxide antifuse dielectric layer over the first electrode, and forming a second electrode over the at least one nonvolatile memory cell. In use, the diode acts as a read/write element of the nonvolatile memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.
摘要翻译：一种制造非易失性存储器件的方法包括：形成第一电极，在所述第一电极上形成至少一个包括二极管和金属氧化物反熔丝电介质层的非易失性存储单元，以及在所述至少一个非易失性存储单元上形成第二电极。在使用中，响应于施加的偏压，二极管通过从第一电阻率状态切换到不同于第一电阻率状态的第二电阻率状态来充当非易失性存储单元的读/写元件。

89. 发明申请

US20080311710A1 METHOD TO FORM LOW-DEFECT POLYCRYSTALLINE SEMICONDUCTOR MATERIAL FOR USE IN A TRANSISTOR 有权
标题翻译：形成用于晶体管的低缺陷多晶半导体材料的方法
公开(公告)号：US20080311710A1
公开(公告)日：2008-12-18
申请号：US11763671
申请日：2007-06-15
申请人： S. Brad Herner , Christopher J. Petti
发明人： S. Brad Herner , Christopher J. Petti
IPC分类号： H01L21/336 , H01L21/331
CPC分类号： H01L27/24 , H01L21/8221 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/11578 , H01L27/12 , H01L27/1277 , H01L29/6675 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A method is described for forming a thin film transistor having its current-switching region in polycrystalline semiconductor material which has been crystallized in contact with titanium silicide, titanium silicide-germanide, or titanium germanide. The titanium silicide, titanium silicide-germanide, or titanium germanide is formed having feature size no more than 0.25 micron in the smallest dimension. The small feature size tends to inhibit the phase transformation from C49 to C54 phase titanium silicide. The C49 phase of titanium silicide has a very close lattice match to silicon, and thus provides a crystallization template for the silicon as it forms, allowing formation of large-grain, low-defect silicon. Titanium does not tend to migrate through the silicon during crystallization, limiting the danger of metal contamination. In preferred embodiments, the transistors thus formed may be, for example, field-effect transistors or bipolar junction transistors.
摘要翻译：描述了一种用于形成其多晶半导体材料中具有电流切换区域的薄膜晶体管的方法，其已经与硅化钛，硅化钛 - 锗化锗或锗化锗接触而结晶化。在最小尺寸上形成特征尺寸不超过0.25微米的硅化钛，硅化钛 - 锗化锗或锗锗。小特征尺寸倾向于抑制从C49到C54相钛硅化物的相变。硅化钛的C49相具有与硅非常接近的晶格匹配，因此在形成硅时提供了硅的结晶模板，从而形成大晶粒，低缺陷硅。在结晶过程中，钛不会通过硅迁移，限制了金属污染的危险。在优选实施例中，如此形成的晶体管可以是例如场效应晶体管或双极结型晶体管。

90. 发明申请

US20080237599A1 MEMORY CELL COMPRISING A CARBON NANOTUBE FABRIC ELEMENT AND A STEERING ELEMENT 有权
标题翻译：包含碳纳米管织物元件和转向元件的存储单元
公开(公告)号：US20080237599A1
公开(公告)日：2008-10-02
申请号：US11692148
申请日：2007-03-27
申请人： S. Brad Herner , Roy E. Scheuerlein
发明人： S. Brad Herner , Roy E. Scheuerlein
IPC分类号： H01L27/10 , H01L29/04
CPC分类号： H01L27/101 , B82Y10/00 , G11C13/025 , G11C2213/71 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/149
摘要： A rewritable nonvolatile memory cell is disclosed comprising a steering element in series with a carbon nanotube fabric. The steering element is preferably a diode, but may also be a transistor. The carbon nanotube fabric reversibly changes resistivity when subjected to an appropriate electrical pulse. The different resistivity states of the carbon nanotube fabric can be sensed, and can correspond to distinct data states of the memory cell. A first memory level of such memory cells can be monolithically formed above a substrate, a second memory level monolithically formed above the first, and so on, forming a highly dense monolithic three dimensional memory array of stacked memory levels.
摘要翻译：公开了一种可重写的非易失性存储单元，其包括与碳纳米管织物串联的转向元件。转向元件优选为二极管，但也可以是晶体管。当经受适当的电脉冲时，碳纳米管织物可逆地改变电阻率。可以感测碳纳米管织物的不同电阻率状态，并且可以对应于存储器单元的不同数据状态。这种存储器单元的第一存储器级别可以单片地形成在衬底上方，第一存储器级单元形成在第一存储器之上，等等，形成堆叠存储器级别的高密度单片三维存储器阵列。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式