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81. 发明授权

US08377814B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08377814B2
公开(公告)日：2013-02-19
申请号：US13164931
申请日：2011-06-21
申请人： Atsuhiro Sato , Hiroyuki Nitta , Fumitaka Arai
发明人： Atsuhiro Sato , Hiroyuki Nitta , Fumitaka Arai
IPC分类号： H01L21/28
CPC分类号： H01L27/11524 , H01L21/76816 , H01L27/11521
摘要： A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.
摘要翻译：半导体存储器件包括具有第一存储器单元和第一选择晶体管的第一块，具有第二存储单元和第二选择晶体管的第二块，并且沿第一方向布置成与第一块相邻，第二选择晶体管被布置为面对第一选择晶体管，并且通常具有与第一选择晶体管的扩散区，第一互连层，设置在第一和第二块之间的扩散区上并沿第二方向延伸;第二互连层，具有设置成与第一选择晶体管接触的第一部分第一互连层的上部并且延伸到第一互连层外部的部分，以及第二部分，其在第二方向上延伸并且在第一互连层上的部分外部的部分连接到第一部分。

82. 发明授权

US08377720B2 Method of manufacturing a semiconductor device including an insulating film beside an element isolation film 失效
标题翻译：制造包括元件隔离膜旁边的绝缘膜的半导体器件的方法
公开(公告)号：US08377720B2
公开(公告)日：2013-02-19
申请号：US11419079
申请日：2006-05-18
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Hiroyuki Nitta
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Hiroyuki Nitta
IPC分类号： H01L21/00
CPC分类号： H01L27/088 , H01L21/823857 , H01L21/823892 , H01L27/0207 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： A method of manufacturing a semiconductor device involves process for forming gate insulating films of different thickness on a semiconductor substrate, depositing films that constitute a gate electrode, removing the gate insulating films having different thickness formed on an impurity diffusion region surface of a transistor including the gate electrode, and doping impurities into a portion where the gate insulating film is removed.
摘要翻译：半导体器件的制造方法包括在半导体衬底上形成不同厚度的栅极绝缘膜的工艺，沉积构成栅电极的膜，去除在包括晶体管的晶体管的杂质扩散区域表面上形成的具有不同厚度的栅极绝缘膜栅极电极和将杂质掺杂到去除栅极绝缘膜的部分中。

83. 发明授权

US08349686B2 Nonvolatile semiconductor memory device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08349686B2
公开(公告)日：2013-01-08
申请号：US13197580
申请日：2011-08-03
申请人： Hiroyuki Nitta
发明人： Hiroyuki Nitta
IPC分类号： H01L21/00
CPC分类号： H01L27/11524 , H01L21/764 , H01L23/5222 , H01L27/11521 , H01L2924/0002 , H01L2924/00
摘要： To reduce capacitance between each adjacent two word lines in a semiconductor memory device, a first insulating film is formed, with a first gate insulating film thereunder, in an interstice between gates respectively of each adjacent two memory transistors, and in an interstice between a gate of a selective transistor and a gate of a memory transistor adjacent thereto. Additionally, a second insulating film is formed on the first insulating film, sides of the gate of each memory transistor, and a side, facing the memory transistor, of the gate of the selective transistor. A third insulating film is formed parallel to a semiconductor substrate so as to cover a metal silicide film, the first and second insulating films and fourth and fifth insulating films. Avoid part is provided in the interstice between each adjacent two gates of the memory transistors, and in the interstice between the gate of the selective transistor and the gate of the memory transistor adjacent thereto. A bottom and two sides of each void part are shielded by the second insulating film, and a top of each void part is shielded by the third insulating film.
摘要翻译：为了减小半导体存储器件中每个相邻两个字线之间的电容，在每个相邻的两个存储晶体管的栅极之间的间隙中形成第一绝缘膜，其间具有第一栅极绝缘膜，并且在栅极的选择晶体管和与其相邻的存储晶体管的栅极。此外，第二绝缘膜形成在第一绝缘膜上，每个存储晶体管的栅极的侧面和面向存储晶体管的选择性晶体管的栅极的一侧。第三绝缘膜平行于半导体衬底形成以覆盖金属硅化物膜，第一和第二绝缘膜以及第四和第五绝缘膜。避免在存储晶体管的每个相邻两个栅极之间的间隙中以及选择性晶体管的栅极和与其相邻的存储晶体管的栅极之间的间隙中提供部件。每个空隙部分的底部和两侧被第二绝缘膜屏蔽，并且每个空隙部分的顶部被第三绝缘膜屏蔽。

84. 发明授权

US08345072B2 Display system 有权
标题翻译：显示系统
公开(公告)号：US08345072B2
公开(公告)日：2013-01-01
申请号：US13423315
申请日：2012-03-19
申请人： Yoshiki Kurokawa , Yasuyuki Kudo , Hiroyuki Nitta , Kazuki Homma , Junya Takeda
发明人： Yoshiki Kurokawa , Yasuyuki Kudo , Hiroyuki Nitta , Kazuki Homma , Junya Takeda
IPC分类号： G09G5/00 , G09G5/02 , G06T1/00 , G06K9/00 , G06K9/40 , H04N1/60 , H04N1/46
CPC分类号： G09G1/002 , G09G3/3655 , G09G5/04 , G09G5/06 , G09G2320/0242 , G09G2340/145
摘要： A display drive circuit of the invention has: an initial-color-gamut-apex-coordinate-storing unit capable of storing initial color gamut apex coordinates; a user-target-color-gamut-apex-coordinate-storing unit capable of storing user target color gamut apex coordinates; a saturation-expansion-coefficient-deciding unit for deciding expansion coefficients of saturation data based on the initial and user target color gamut apex coordinates; and an expansion unit for expanding saturations of display data based on the saturation expansion coefficients. The expansion coefficients of saturation data are decided based on the initial and user target color gamut apex coordinates, and saturations of display data are expanded according to the expansion coefficients. Thus, the degree of expanding the saturations can be controlled for each color gamut or each of R, G and B color properties of an LC display panel.
摘要翻译：本发明的显示驱动电路具有：能够存储初始色域顶点坐标的初始色域 - 顶点坐标存储单元; 能够存储用户目标色域顶点坐标的用户对象色彩 - 顶点坐标存储单元; 饱和扩张系数决定单元，用于基于初始和用户目标色域顶点坐标来确定饱和度数据的扩展系数; 以及用于基于饱和度膨胀系数扩大显示数据的饱和度的扩展单元。基于初始和用户目标色域顶点坐标来确定饱和度数据的扩展系数，根据扩展系数扩展显示数据的饱和度。因此，可以对于每个色域或LC显示面板的R，G和B颜色属性中的每一个来控制饱和度的扩大程度。

85. 发明申请

US20120126306A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件的非易失性存储器件和制造方法
公开(公告)号：US20120126306A1
公开(公告)日：2012-05-24
申请号：US13238380
申请日：2011-09-21
申请人： Genki KAWAGUCHI , Fumitaka Arai , Satoshi Nagashima , Naoki Kai , Wataru Sakamoto , Hiroyuki Nitta
发明人： Genki KAWAGUCHI , Fumitaka Arai , Satoshi Nagashima , Naoki Kai , Wataru Sakamoto , Hiroyuki Nitta
IPC分类号： H01L29/788 , H01L21/28 , H01L29/792
CPC分类号： H01L27/11524 , H01L21/764 , H01L21/7682 , H01L27/11529 , H01L29/42376
摘要： According to one embodiment, a memory cell includes a charge storage layer. A first air gap is provided between charge storage layers adjacent in a word line direction. A second air gap is provided between charge storage layers adjacent in a bit line direction.
摘要翻译：根据一个实施例，存储单元包括电荷存储层。在字线方向相邻的电荷存储层之间设置第一气隙。在位线方向相邻的电荷存储层之间提供第二气隙。

86. 发明申请

US20120020158A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120020158A1
公开(公告)日：2012-01-26
申请号：US13187000
申请日：2011-07-20
申请人： Tohru OZAKI , Mitsuhiro Noguchi , Hideaki Maekawa , Hiromitsu Mashita , Takafumi Taguchi , Kazuhito Kobayashi , Hidefumi Mukai , Hiroyuki Nitta
发明人： Tohru OZAKI , Mitsuhiro Noguchi , Hideaki Maekawa , Hiromitsu Mashita , Takafumi Taguchi , Kazuhito Kobayashi , Hidefumi Mukai , Hiroyuki Nitta
IPC分类号： G11C16/04 , H01L21/78
CPC分类号： H01L27/11521
摘要： A memory cell array includes memory strings arranged in a first direction. Word-lines and select gate lines extend in a second direction perpendicular to the first direction. The select gate line also extends in the second direction. The word-lines have a first line width in the first direction and arranged with a first distance therebetween. The select gate line includes a first interconnection in the first direction, the first interconnection having a second line width larger than the first line width, and a second interconnection extending from an end portion of the first interconnection, the second interconnection having a third line width the same as the first line width. A first word-line adjacent to the select gate line is arranged having a second distance to the second interconnection, the second distance being (4N+1) times the first distance (N being an integer of 1 or more).
摘要翻译：存储单元阵列包括沿第一方向布置的存储器串。字线和选择栅极线在垂直于第一方向的第二方向上延伸。选择栅极线也沿第二方向延伸。字线在第一方向上具有第一线宽度并且以它们之间的第一距离布置。选择栅极线包括在第一方向上的第一互连，第一互连具有大于第一线宽的第二线宽，以及从第一互连的端部延伸的第二互连，第二互连具有第三线宽与第一行宽度相同。与选择栅极线相邻的第一字线布置成具有到第二互连的第二距离，第二距离为（4N + 1）倍于第一距离（N为1或更大的整数）。

87. 发明授权

US07847771B2 Display device capable of adjusting divided data in one frame 有权
标题翻译：能够在一帧中调整分割数据的显示装置
公开(公告)号：US07847771B2
公开(公告)日：2010-12-07
申请号：US11279598
申请日：2006-04-13
申请人： Junichi Maruyama , Hiroyuki Nitta , Yoshihisa Ooishi , Kikuo Ono
发明人： Junichi Maruyama , Hiroyuki Nitta , Yoshihisa Ooishi , Kikuo Ono
IPC分类号： G09G3/36
CPC分类号： G09G3/2022 , G09G3/3688 , G09G2320/0252 , G09G2320/0261 , G09G2320/0276 , G09G2340/16
摘要： A speed doubling circuit receiving display data in one frame period and outputting field A display data and field B display data in one frame period. A field conversion circuit converts the field A display data to have a highest gray-scale if the display data has a high gray-scale, and converts the field B display data to have a lowest gray-scale if the display data has a low gray-scale. Between the speed doubling circuit and field conversion circuit, an emphasis circuit is disposed which emphasizes each of the field A display data and field B display data in accordance with the display data one frame period before and the display data in the present frame period.
摘要翻译：在一个帧周期中接收显示数据并在一个帧周期中输出字段A显示数据和字段B显示数据的加倍电路。如果显示数据具有高灰阶，则场转换电路将场A显示数据转换为具有最高灰度，并且如果显示数据具有低灰度，则将场B显示数据转换为具有最低灰度 -规模。在倍速电路和场转换电路之间，设置强调电路，其根据前一帧周期的显示数据和当前帧周期中的显示数据强调场A显示数据和场B显示数据中的每一个。

88. 发明申请

US20100052017A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20100052017A1
公开(公告)日：2010-03-04
申请号：US12553496
申请日：2009-09-03
申请人： Atsuhiro SATO , Hiroyuki Nitta , Fumitaka Arai
发明人： Atsuhiro SATO , Hiroyuki Nitta , Fumitaka Arai
IPC分类号： H01L29/66 , H01L21/4763
CPC分类号： H01L27/11524 , H01L21/76816 , H01L27/11521
摘要： A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.
摘要翻译：半导体存储器件包括具有第一存储器单元和第一选择晶体管的第一块，具有第二存储单元和第二选择晶体管的第二块，并且沿第一方向布置成与第一块相邻，第二选择晶体管被布置为面对第一选择晶体管，并且通常具有与第一选择晶体管的扩散区，第一互连层，设置在第一和第二块之间的扩散区上并沿第二方向延伸;第二互连层，具有设置成与第一选择晶体管接触的第一部分第一互连层的上部并且延伸到第一互连层外部的部分，以及第二部分，其在第二方向上延伸并且在第一互连层上的部分外部的部分连接到第一部分。

89. 发明授权

US07184356B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07184356B2
公开(公告)日：2007-02-27
申请号：US11074801
申请日：2005-03-09
申请人： Mitsuhiro Noguchi , Akira Goda , Hiroyuki Nitta
发明人： Mitsuhiro Noguchi , Akira Goda , Hiroyuki Nitta
IPC分类号： G11C8/00
CPC分类号： G06F11/1008 , G06F11/108 , G11C7/22 , G11C16/04 , G11C16/0483 , G11C16/26 , G11C16/32 , G11C16/3454 , G11C29/50004 , G11C29/52 , G11C29/76 , G11C29/82 , G11C29/84 , G11C2029/0409 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device includes: a memory cell array having a plurality of data select lines disposed in parallel with each other, a plurality of data transfer line disposed in parallel with each other to intersect the data select lines, and electrically rewritable memory cells laid out at cross portions between the data select lines and data transfer lines; a data select line driver for driving the data select lines of the memory cell array; a sense amplifier circuit connected to the data transfer lines of the memory cell array, for performing data read of memory cells selected by one of the data select lines; and a control circuit used for timing control of data read of the memory cell array, for outputting at least two types of timing signals as being different in accordance with a selected data area of the memory cell array.
摘要翻译：半导体存储器件包括：存储单元阵列，具有彼此平行布置的多个数据选择线;多个数据传输线，彼此并联设置，以与数据选择线相交;以及布置的电可重写存储器单元在数据选择线和数据传输线之间的交叉部分; 用于驱动存储单元阵列的数据选择线的数据选择线驱动器; 连接到存储单元阵列的数据传输线的读出放大器电路，用于对数据选择线之一选择的存储器单元执行数据读取; 以及用于对存储单元阵列的数据读取进行定时控制的控制电路，用于根据存储单元阵列的所选择的数据区输出不同的至少两种类型的定时信号。

90. 发明授权

US07173594B2 Display device and driving method thereof 有权
标题翻译：显示装置及其驱动方法
公开(公告)号：US07173594B2
公开(公告)日：2007-02-06
申请号：US10760362
申请日：2004-01-21
申请人： Masashi Nakamura , Hiroyuki Nitta , Nobuhiro Takeda , Masahiro Tanaka
发明人： Masashi Nakamura , Hiroyuki Nitta , Nobuhiro Takeda , Masahiro Tanaka
IPC分类号： G09G3/36 , G09G5/00
CPC分类号： G09G3/3648 , G09G3/30 , G09G2300/08 , G09G2310/062 , G09G2320/0261
摘要： A data driver of a display device alternately repeats a first step of sequentially generating a display signal corresponding to each one of the lines of image data for a fixed period and outputting the display signal to a pixel array N-times and a second step of generating a display signal which makes the luminance of pixels lower than the luminance of the pixel in the first step for the fixed period and of outputting the display signal to the pixel array M-times. A scanning driver circuit alternately repeats selecting a plurality of pixel rows for every Y rows sequentially from one end to another end of the pixel array along the second direction in the first step and selecting the plurality of pixel rows other than the pixel rows (Y×N) sequentially from one end to another end of the pixel array for every Z rows along the second direction.
摘要翻译：显示装置的数据驱动器交替地重复第一步骤，在固定周期内顺序地生成与图像数据中的每一行相对应的显示信号，并将显示信号输出到像素阵列N次，并产生第二步骤显示信号，其使像素的亮度低于第一步骤中的像素的亮度，并将该显示信号输出到像素阵列M次。扫描驱动器电路在第一步骤中沿着第二方向交替地重复从像素阵列的一端到另一端依次选择每Y行的多个像素行，并且选择除了像素行（YxN）之外的多个像素行，沿着第二方向对于每Z列依次从像素阵列的一端到另一端。

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