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81. 发明授权

US06362650B1 Method and apparatus for incorporating a multiplier into an FPGA 有权
标题翻译：将乘法器并入到FPGA中的方法和装置
公开(公告)号：US06362650B1
公开(公告)日：2002-03-26
申请号：US09574714
申请日：2000-05-18
申请人： Bernard J. New , Steven P. Young
发明人： Bernard J. New , Steven P. Young
IPC分类号： H03K19177
CPC分类号： G06F15/7867 , G06F7/523 , G06F17/5054 , H03K19/17732 , H03K19/1776
摘要： One or more columns of multi-function tiles are positioned between CLB tiles of the FPGA array. Each multi-function tile includes multiple function elements that share routing resources. In one embodiment, a multi-function tile includes a configurable, dual-ported RAM and a multiplier that share routing resources of the multi-function tile. The RAM includes first and second input ports coupled to first and second input data buses, respectively, and includes first and second output ports coupled to first and second output data buses, respectively. The multiplier includes first and second operand ports coupled to receive operands from the first and second input data buses, and in response thereto provides a product. In one embodiment, the most significant bits (MSBs) of the product are selectively provided to the first output data bus using bus multiplexer logic, and the least significant bits (LSBs) of the product are selectively provided to the second output data bus using bus multiplexer logic.
摘要翻译：一列或多列多功能瓦片位于FPGA阵列的CLB瓦片之间。每个多功能瓦片包括共享路由资源的多个功能元件。在一个实施例中，多功能瓦片包括可配置的双端口RAM和共享多功能瓦片的路由资源的乘法器。 RAM包括分别耦合到第一和第二输入数据总线的第一和第二输入端口，并且分别包括耦合到第一和第二输出数据总线的第一和第二输出端口。乘法器包括耦合以从第一和第二输入数据总线接收操作数的第一和第二操作数端口，并且响应于此提供产品。在一个实施例中，使用总线复用器逻辑将产品的最高有效位（MSB）选择性地提供给第一输出数据总线，并且使用总线选择性地将产品的最低有效位（LSB）提供给第二输出数据总线多路复用逻辑

82. 发明授权

US06294930B1 FPGA with a plurality of input reference voltage levels 有权
标题翻译： FPGA具有多个输入参考电压电平
公开(公告)号：US06294930B1
公开(公告)日：2001-09-25
申请号：US09479392
申请日：2000-01-06
申请人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
发明人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
IPC分类号： G06F738
CPC分类号： H03K19/17744 , H03K19/00361 , H03K19/1778 , H03K19/17788
摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.
摘要翻译：本发明包括具有多个输入参考电压和/或输出电压源的FPGA。在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。根据本发明的另一方面，将单个输入参考电压和/或单个输出电压电源应用于每个IOB，其中IOB被分组成组。每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

83. 发明授权

US5877632A FPGA with a plurality of I/O voltage levels 失效
标题翻译：具有多个I / O电压电平的FPGA
公开(公告)号：US5877632A
公开(公告)日：1999-03-02
申请号：US837023
申请日：1997-04-11
申请人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
发明人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
IPC分类号： G06F7/38 , H03K19/003 , H03K19/094 , H03K19/177 , H03K19/0948
CPC分类号： H03K19/17744 , H03K19/00361 , H03K19/1778 , H03K19/17788
摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines.
摘要翻译：本发明包括具有多个输入参考电压和/或输出电压源的FPGA。在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。

84. 发明授权

US5294830A Apparatus for indirect impingement cooling of integrated circuit chips 失效
标题翻译：用于集成电路芯片的间接冲击冷却的装置
公开(公告)号：US5294830A
公开(公告)日：1994-03-15
申请号：US703614
申请日：1991-05-21
申请人： Steven P. Young , John Acocella , Albert J. Fahey , Gaetano P. Messina , Seaho Song
发明人： Steven P. Young , John Acocella , Albert J. Fahey , Gaetano P. Messina , Seaho Song
IPC分类号： H01L23/433 , H01L23/473 , H01L23/02 , H01L25/04
CPC分类号： H01L23/4735 , H01L23/4338 , H01L2224/16225 , H01L2924/15312
摘要： An integrated circuit thermal conduction module comprises a substrate having a chip-carrying surface and at least one integrated circuit chip on the substrate. A deformable, liquid-impermeable, thermally conductive film or foil extends over an upper surface of the chip. A piston has a lower surface which urges and conforms the film against the chip upper surface and which contains at least one open channel permitting coolant passage and contact with the film for conveying heat from the chip without direct contact between the coolant and chip. Preferably, the piston has a central passageway extending along the longitudinal axis for channeling the coolant through the piston, and has a plurality of channels extending radially outwardly from the central passageway along the lower face for directing coolant beneath the piston.
摘要翻译：集成电路热传导模块包括具有芯片承载表面的衬底和在衬底上的至少一个集成电路芯片。可变形的液体不可渗透的导热膜或箔在芯片的上表面上延伸。活塞具有下表面，该下表面促使薄膜抵靠芯片上表面，并且其包含至少一个敞开的通道，允许冷却剂通过并与薄膜接触，用于从芯片传送热量，而不会直接接触冷却剂和芯片。优选地，活塞具有沿着纵向轴线延伸的中心通道，用于将冷却剂引导通过活塞，并且具有沿着下表面从中心通道径向向外延伸的多个通道，用于将冷却剂引导到活塞下方。

85. 发明授权

US5130067A Method and means for co-sintering ceramic/metal MLC substrates 失效
标题翻译：用于共烧陶瓷/金属MLC衬底的方法和手段
公开(公告)号：US5130067A
公开(公告)日：1992-07-14
申请号：US859093
申请日：1986-05-02
申请人： Philip L. Flaitz , Arlyne M. Flanagan , Joseph M. Harvilchuck , Lester W. Herron , John U. Knickerbocker , Robert W. Nufer , Charles H. Perry , Srinivasa N. Reddy , Steven P. Young
发明人： Philip L. Flaitz , Arlyne M. Flanagan , Joseph M. Harvilchuck , Lester W. Herron , John U. Knickerbocker , Robert W. Nufer , Charles H. Perry , Srinivasa N. Reddy , Steven P. Young
IPC分类号： C04B35/638 , C04B35/64 , H01L21/48
CPC分类号： C04B35/64 , C04B35/638 , H01L21/4807
摘要： A method for co-sintering ceramic/metal multi-layered ceramic substrates wherein X-Y shrinkage is controlled and X-Y distortion and Z-direction chamber are substantially eliminated. Binder-burnoff is substantially not aggravated during this process as well. The process is accomplished by applying selective forces to the surfaces of the ceramic substrates to control lateral movement while allowing Z direction shrinkage movement. Frictional force means, pneumatic forced means and weights are among the means used to supply forces. Cerium oxide is used in certain embodiments to enhance binder-burnoff.
摘要翻译：一种陶瓷/金属多层陶瓷基板的共烧结方法，其中X-Y收缩被控制，并且基本上消除了X-Y变形和Z方向室。在此过程中，粘结剂 - 烧毁也基本上不会加剧。该过程通过向陶瓷基底的表面施加选择力来实现，以控制横向运动，同时允许Z方向收缩运动。摩擦力意味着，气动强制手段和重量是用于供应力的手段之一。在某些实施方案中使用氧化铈以增强粘合剂 - 燃烧。

86. 发明授权

US08527572B1 Multiplier architecture utilizing a uniform array of logic blocks, and methods of using the same 有权
标题翻译：利用统一的逻辑块阵列的乘法体系结构及其使用方法
公开(公告)号：US08527572B1
公开(公告)日：2013-09-03
申请号：US12417007
申请日：2009-04-02
申请人： Steven P. Young , Brian C. Gaide
发明人： Steven P. Young , Brian C. Gaide
IPC分类号： G06F7/52
CPC分类号： G06F7/5324 , G06F7/00 , G06F7/49994 , G06F7/57 , G06F2207/3864
摘要： In a multiplier architecture, all stages of a multiplication function are implemented using a uniform array of logic blocks. An exemplary multiplier circuit includes a two-dimensional array of substantially similar logic blocks. Each logic block includes a multiply block and a logic circuit driven by the multiply block. The logic circuit is coupled to implement an add function. A first portion of the array is coupled to receive the first and second multiplicand inputs, to provide a partial product bus, and to provide lower bits of the product output. A second portion is coupled to receive the partial product bus from the first portion of the array, and to provide from the partial product bus upper bits of the product output. The multiply blocks may be non-uniform arrays, e.g., logical AND gates and full adders in all but one column, with only logical AND gates in the remaining column.
摘要翻译：在乘法器架构中，乘法函数的所有阶段都使用统一的逻辑块阵列来实现。示例性乘法器电路包括基本相似的逻辑块的二维阵列。每个逻辑块包括乘法块和乘法块驱动的逻辑电路。逻辑电路被耦合以实现加法功能。阵列的第一部分被耦合以接收第一和第二被乘数输入，以提供部分乘积总线，并提供产品输出的较低位。第二部分被耦合以从阵列的第一部分接收部分乘积总线，并且从部分乘积总线提供产品输出的较高位。乘法块可以是除了一列之外的不均匀的阵列，例如逻辑与门和全加法器，在剩余的列中只有逻辑与门。

87. 发明授权

US08495122B2 Programmable device with dynamic DSP architecture 有权
标题翻译：具有动态DSP架构的可编程器件
公开(公告)号：US08495122B2
公开(公告)日：2013-07-23
申请号：US11019735
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/38
CPC分类号： H03K19/17736 , H03K19/17732
摘要： Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each slice includes a mode port that receives mode control signals for dynamically altering the function and connectivity of related slices. Such alterations can occur with or without reconfiguring the PLD.
摘要翻译：描述了可编程逻辑器件（PLD），其具有可以级联的DSP片段，以创建不同大小和复杂度的DSP电路。每个片包括一个模式端口，它接收模式控制信号，用于动态地改变相关片段的功能和连通性。这种改变可以在或不配置PLD的情况下发生。

88. 发明申请

US20110147949A1 HYBRID INTEGRATED CIRCUIT DEVICE 有权
标题翻译：混合集成电路设备
公开(公告)号：US20110147949A1
公开(公告)日：2011-06-23
申请号：US13038746
申请日：2011-03-02
申请人： James Karp , Steven P. Young , Bernard J. New , Scott S. Nance , Patrick J. Crotty
发明人： James Karp , Steven P. Young , Bernard J. New , Scott S. Nance , Patrick J. Crotty
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H03K19/177 , G06F17/5068 , H01L24/48 , H01L25/0657 , H01L2224/05553 , H01L2224/16145 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2924/00014 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/19041 , H01L2924/37001 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An embodiment of a method to form a hybrid integrated circuit device is described. This embodiment of the method comprises: forming a first die using a first lithography, where the first die is on a substrate; and forming a second die using a second lithography, where the second die is on the first die. The first lithography used to form the first die is a larger lithography than the second lithography used to form the second die. The first die is an IO die.
摘要翻译：描述形成混合集成电路器件的方法的实施例。该方法的该实施例包括：使用第一光刻形成第一裸片，其中第一裸片位于衬底上; 以及使用第二光刻形成第二管芯，其中所述第二管芯位于所述第一管芯上。用于形成第一裸片的第一光刻是比用于形成第二裸片的第二光刻更大的光刻。第一个模具是IO模具。

89. 发明授权

US07919845B2 Formation of a hybrid integrated circuit device 有权
标题翻译：形成混合集成电路器件
公开(公告)号：US07919845B2
公开(公告)日：2011-04-05
申请号：US12004906
申请日：2007-12-20
申请人： James Karp , Steven P. Young , Bernard J. New , Scott S. Nance , Patrick J. Crotty
发明人： James Karp , Steven P. Young , Bernard J. New , Scott S. Nance , Patrick J. Crotty
IPC分类号： H01L23/02
CPC分类号： H03K19/177 , G06F17/5068 , H01L24/48 , H01L25/0657 , H01L2224/05553 , H01L2224/16145 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2924/00014 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/19041 , H01L2924/37001 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Formation of a hybrid integrated circuit device is described. A design for the integrated circuit is obtained and separated into at least two portions responsive to component sizes. A first die is formed for a first portion of the hybrid integrated circuit device using at least in part a first minimum dimension lithography. A second die is formed for a second portion of the device using at least in part a second minimum dimension lithography, where the second die has the second minimum dimension lithography as a smallest lithography used for the forming of the second die. The first die and the second die are attached to one another via coupling interconnects respectively thereof to provide the hybrid integrated circuit device.
摘要翻译：描述了混合集成电路器件的形成。获得集成电路的设计并将其分离成响应于部件尺寸的至少两个部分。使用至少部分第一最小尺寸光刻形成用于混合集成电路器件的第一部分的第一裸片。使用至少部分第二最小尺寸光刻形成用于装置的第二部分的第二模具，其中第二模具具有作为用于形成第二模具的最小光刻的第二最小尺寸光刻。第一管芯和第二管芯分别通过其耦合互连件彼此附接以提供混合集成电路器件。

90. 发明授权

US07746112B1 Output structure with cascaded control signals for logic blocks in integrated circuits, and methods of using the same 有权
标题翻译：集成电路中用于逻辑块的级联控制信号的输出结构及其使用方法
公开(公告)号：US07746112B1
公开(公告)日：2010-06-29
申请号：US12417043
申请日：2009-04-02
申请人： Brian C. Gaide , Steven P. Young
发明人： Brian C. Gaide , Steven P. Young
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , H03K19/17736
摘要： A cascading output structure for logic blocks in an integrated circuit. An exemplary integrated circuit includes an array of interconnected logic blocks, each including a logic circuit, an output multiplexer, and a select multiplexer. The logic circuit has an input coupled to a logic block input. The output multiplexer has first and second data inputs respectively coupled to first and second outputs of the logic circuit, a select input, and an output coupled to a logic block output. The select multiplexer has a first data input coupled to a cascade select input of the logic block, a second data input, and an output coupled to the select input of the output multiplexer. The output of the select multiplexer is also coupled to a cascade select output of the logic block. The cascade select input of the logic block is coupled to the cascade select output of an adjacent logic block.
摘要翻译：集成电路中逻辑块的级联输出结构。示例性集成电路包括互连的逻辑块的阵列，每个逻辑块包括逻辑电路，输出多路复用器和选择多路复用器。逻辑电路具有耦合到逻辑块输入的输入。输出多路复用器具有分别耦合到逻辑电路的第一和第二输出的第一和第二数据输入，选择输入和耦合到逻辑块输出的输出。选择多路复用器具有耦合到逻辑块的级联选择输入的第一数据输入，第二数据输入和耦合到输出多路复用器的选择输入的输出。选择多路复用器的输出也耦合到逻辑块的级联选择输出。逻辑块的级联选择输入耦合到相邻逻辑块的级联选择输出。

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