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    • 82. 发明授权
    • Hot water supply system
    • 热水供应系统
    • US4449484A
    • 1984-05-22
    • US444367
    • 1982-11-26
    • Moriyoshi SakamotoToshihiko Saito
    • Moriyoshi SakamotoToshihiko Saito
    • F23C15/00F24H1/20F24H9/18F22B5/00
    • F23C15/00F24H1/206
    • A hot water supply system comprises a base of cylindrical shape; a storage tank supported on the base, the tank having an upper end plate and a lower end plate supported on the base and defining, together with an inner face of the base, a soundproofing chamber; and a pulse combustor including a pulse burner attached to the lower end plate, and a tail pipe which communicates with the burner and is arranged inside the storage tank next to the lower end plate, the tail pipe having an ascending portion extending from the pulse burner toward the upper end plate, and a descending portion extending from a top end of the ascending portion toward the lower end plate to guide condensed water condensed inside the tail pipe to outside the storage tank. The system further comprises a blower, a suction muffler, and an exhaust muffler which are arranged inside the soundproofing chamber, the base having a soundproofing layer to shield noise generated in the soundproofing chamber.
    • 热水供应系统包括圆柱形基座; 支撑在基座上的储罐,该罐具有支撑在基座上的上端板和下端板,并与基座的内表面一起限定隔音室; 以及包括安装在下端板上的脉冲燃烧器的脉冲燃烧器,以及与燃烧器连通并设置在储罐内部的下端板旁边的尾管,尾管具有从脉冲燃烧器延伸的上升部 以及从上升部的顶端朝向下端板延伸的下降部,以将在尾管内凝结的冷凝水引导到储罐外。 该系统还包括布置在隔音室内部的鼓风机,吸入消声器和排气消声器,底座具有隔音层,用于屏蔽隔音室中产生的噪声。
    • 85. 发明授权
    • Pulse converter circuit
    • 脉冲变换电路
    • US09209206B2
    • 2015-12-08
    • US13107167
    • 2011-05-13
    • Toshihiko Saito
    • Toshihiko Saito
    • H03K3/017H01L27/12H01L29/786
    • H03K5/04H01L27/092H01L27/1233H01L27/1237H01L27/1251H01L29/7869
    • A pulse converter circuit includes a logic circuit to which a first signal is input and from which a second signal is output. The logic circuit includes a p-channel transistor which determines whether a voltage of the second signal is set to a first voltage depending on a voltage of the gate; and an n-channel transistor which determines whether the voltage of the second signal is set to a second voltage, which is higher than the first voltage, depending on a voltage of the gate. The p-channel transistor includes a semiconductor layer containing an element of a group 14. The n-channel transistor includes an oxide semiconductor layer.
    • 脉冲转换器电路包括输入第一信号并输出​​第二信号的逻辑电路。 逻辑电路包括一个p沟道晶体管,它确定第二个信号的电压是否根据栅极的电压被设置为第一个电压; 以及n沟道晶体管,其根据栅极的电压确定第二信号的电压是否被设定为高于第一电压的第二电压。 p沟道晶体管包括含有组14的元件的半导体层.n沟道晶体管包括氧化物半导体层。
    • 87. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08797785B2
    • 2014-08-05
    • US13293173
    • 2011-11-10
    • Toshihiko Saito
    • Toshihiko Saito
    • G11C11/24
    • G11C11/401G11C5/02G11C5/063G11C8/14
    • Provided is a memory device in which memory capacity per unit area is increased without making the manufacturing process complicated. The memory device includes a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. Each of the plurality of memory cells includes a switching element and a capacitor including a first electrode and a second electrode. In at least one of the plurality of memory cells, in accordance with a potential applied to one of the plurality of word lines, the switching element controls a connection between one of the plurality of bit lines and the first electrode, and the second electrode is connected to another one of the plurality of word lines.
    • 提供了一种在不使制造过程复杂的情况下增加每单位面积的存储容量的存储器件。 存储装置包括多个存储单元,多个字线和多个位线。 多个存储单元中的每一个包括开关元件和包括第一电极和第二电极的电容器。 在多个存储单元中的至少一个存储单元中,根据施加到多个字线之一的电位,开关元件控制多个位线之一与第一电极之间的连接,第二电极为 连接到多个字线中的另一个。
    • 88. 发明授权
    • Oxide semiconductor device including gate trench and isolation trench
    • 氧化物半导体器件包括栅极沟槽和隔离沟槽
    • US08766255B2
    • 2014-07-01
    • US13418558
    • 2012-03-13
    • Atsuo IsobeToshihiko SaitoKiyoshi Kato
    • Atsuo IsobeToshihiko SaitoKiyoshi Kato
    • H01L29/786
    • H01L27/1156H01L21/76232H01L27/1225H01L29/4236
    • A semiconductor device in which improvement of a property of holding stored data can be achieved. Further, power consumption of a semiconductor device is reduced. A transistor in which a wide-gap semiconductor material capable of sufficiently reducing the off-state current of a transistor (e.g., an oxide semiconductor material) in a channel formation region is used and which has a trench structure, i.e., a trench for a gate electrode and a trench for element isolation, is provided. The use of a semiconductor material capable of sufficiently reducing the off-state current of a transistor enables data to be held for a long time. Further, since the transistor has the trench for a gate electrode, the occurrence of a short-channel effect can be suppressed by appropriately setting the depth of the trench even when the distance between the source electrode and the drain electrode is decreased.
    • 一种其中可以实现保持存储数据的性质的改进的半导体器件。 此外,半导体器件的功耗降低。 使用能够充分降低沟道形成区域中的晶体管(例如,氧化物半导体材料)的截止电流的宽间隙半导体材料的晶体管,其具有沟槽结构,即,沟槽结构 栅电极和用于元件隔离的沟槽。 使用能够充分降低晶体管的截止电流的半导体材料能够长时间保持数据。 此外,由于晶体管具有用于栅极电极的沟槽,所以即使当源电极和漏电极之间的距离减小时,也可以通过适当地设置沟槽的深度来抑制短沟道效应的发生。
    • 89. 发明授权
    • Semiconductor memory device and semiconductor device
    • 半导体存储器件和半导体器件
    • US08750022B2
    • 2014-06-10
    • US13079032
    • 2011-04-04
    • Toshihiko SaitoYasuyuki Takahashi
    • Toshihiko SaitoYasuyuki Takahashi
    • G11C7/12
    • G11C7/12H01L27/112H01L27/11206H01L27/1214
    • A semiconductor memory device or a semiconductor device which has high reading accuracy is provided. A bit line, a word line, a memory cell placed in an intersection portion of the bit line and the word line, and a reading circuit electrically connected to the bit line are provided. The memory cell includes a first transistor and an antifuse. The reading circuit includes a pre-charge circuit, a clocked inverter, and a switch. The pre-charge circuit includes a second transistor and a NAND circuit. The semiconductor memory device includes transistor in each of which an oxide semiconductor is used in a channel formation region, as the first transistor and the second transistor.
    • 提供了具有高读取精度的半导体存储器件或半导体器件。 提供位线,字线,放置在位线和字线的交叉部分中的存储单元,以及电连接到位线的读取电路。 存储单元包括第一晶体管和反熔丝。 读取电路包括预充电电路,时钟反相器和开关。 预充电电路包括第二晶体管和NAND电路。 半导体存储器件包括在沟道形成区域中使用氧化物半导体作为第一晶体管和第二晶体管的晶体管。
    • 90. 发明授权
    • Memory device, semiconductor device, and detecting method for defective memory cell in memory device
    • 存储器件,半导体器件和存储器件中的缺陷存储器单元的检测方法
    • US08687411B2
    • 2014-04-01
    • US13344652
    • 2012-01-06
    • Toshihiko Saito
    • Toshihiko Saito
    • G11C11/24
    • G11C11/401G11C11/405G11C29/50016
    • To provide a memory device which can perform verification operation for detecting a memory cell whose data holding time is shorter than a predetermined length, accurately in a short time. Each memory cell includes at least a first capacitor, a second capacitor, and a transistor which functions as a switching element for controlling supply, storage, and release of charge in the first capacitor and the second capacitor. The capacitance of the first capacitor is thousand or more times the capacitance of the second capacitor, preferably ten thousand or more times the capacitance of the second capacitor. In normal operation, charge is stored using the first capacitor and the second capacitor. In performing verification operation for detecting a memory cell whose data holding time is shorter than a predetermined length, charge is stored using the second capacitor.
    • 为了提供一种能够在短时间内准确地进行用于检测数据保持时间短于预定长度的存储单元的验证操作的存储装置。 每个存储单元至少包括第一电容器,第二电容器和用作控制第一电容器和第二电容器中的电荷的供应,存储和释放的开关元件的晶体管。 第一电容器的电容是第二电容器的电容的千倍以上,优选为第二电容器的电容的一倍以上。 在正常操作中,使用第一电容器和第二电容器存储电荷。 在执行用于检测数据保持时间短于预定长度的存储单元的验证操作时,使用第二电容器存储电荷。