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81. 发明申请

US20050122780A1 NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same 有权
标题翻译： NAND存储器阵列结合了各个存储单元的多个写脉冲编程及其操作方法
公开(公告)号：US20050122780A1
公开(公告)日：2005-06-09
申请号：US10729844
申请日：2003-12-05
申请人： En-Hsing Chen , Andrew Walker , Roy Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca Fasoli
发明人： En-Hsing Chen , Andrew Walker , Roy Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca Fasoli
IPC分类号： G11C5/02 , G11C11/56 , G11C16/04 , G11C16/10
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0466 , G11C16/0483
摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
摘要翻译：示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

82. 发明申请

US20050079675A1 Semiconductor device with localized charge storage dielectric and method of making same 有权
公开(公告)号：US20050079675A1
公开(公告)日：2005-04-14
申请号：US10965763
申请日：2004-10-18
申请人： Alper Ilkbahar , Roy Scheuerlein , Andrew Walker , Luca Fasoli
发明人： Alper Ilkbahar , Roy Scheuerlein , Andrew Walker , Luca Fasoli
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L29/792 , H01L21/00 , H01L21/31 , H01L21/469 , H01L21/84
CPC分类号： H01L29/66833 , G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L29/792
摘要： An array of transistors includes a plurality of transistors, a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction. Each transistor includes a source, a drain, a channel and a localized charge storage dielectric. A first transistor of the plurality of transistors and a second transistor of the plurality of transistors share a common source/drain. A first localized charge storage dielectric of the first transistor does not overlap the common source/drain and a second localized charge storage dielectric of the second transistor overlaps the common source/drain.

83. 发明申请

US20050078514A1 Multiple twin cell non-volatile memory array and logic block structure and method therefor 有权
标题翻译：多个单元非易失性存储器阵列及其逻辑块结构及其方法
公开(公告)号：US20050078514A1
公开(公告)日：2005-04-14
申请号：US10675212
申请日：2003-09-30
申请人： Roy Scheuerlein , Luca Fasoli , Mark Johnson
发明人： Roy Scheuerlein , Luca Fasoli , Mark Johnson
IPC分类号： G11C8/10 , G11C8/14 , G11C11/34 , G11C16/10 , G11C16/16
CPC分类号： G11C15/046 , G11C8/10 , G11C8/14 , G11C16/10 , G11C16/16
摘要： Extremely dense memory cell structures provide for new array structures useful for implementing memory and logic functions. An exemplary non-volatile memory array includes a first plurality of X-lines configured to be logically identical in a read mode of operation, and each associated with a first Y-line group numbering at least one Y-line. Each of the first plurality of X-lines may also be associated with a second Y-line group numbering at least one Y-line. In some embodiments, the first and second Y-Line groups are simultaneously selectable in a read mode and, when so selected, are respectively coupled to true and complement inputs of a sense amplifier circuit. Such Y-line groups may number only one Y-line, or may number more than one Y-line. Many types of memory cells may be used, such as various passive element cells and EEPROM cells, in both 2D or 3D memory arrays. Such arrays may be configured as a memory to store data, or configured to perform threshold logic, or configured as a content addressable memory array.
摘要翻译：非常密集的存储单元结构提供了用于实现内存和逻辑功能的新数组结构。示例性非易失性存储器阵列包括被配置为在读取操作模式下在逻辑上相同的第一多个X线，并且每个X线与与至少一个Y线编号的第一Y线组相关联。第一多个X线中的每一个也可以与编号至少一个Y线的第二Y线组相关联。在一些实施例中，第一和第二Y线组可以以读取模式同时选择，并且当这样选择时，它们分别耦合到读出放大器电路的真实和补码输入。这样的Y线组可以仅编号一条Y线，或者可以编号多于一条Y线。可以在2D或3D存储器阵列中使用许多类型的存储单元，例如各种无源元件单元和EEPROM单元。这样的阵列可以被配置为存储数据，或被配置为执行阈值逻辑或被配置为内容可寻址存储器阵列的存储器。

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