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81. 发明授权

US06650093B1 Auxiliary boundary regulator that provides enhanced transient response 有权
标题翻译：辅助边界调节器，提供增强的瞬态响应
公开(公告)号：US06650093B1
公开(公告)日：2003-11-18
申请号：US10162113
申请日：2002-06-03
申请人： Dave Baldwin , Sanmukh Patel , Ross E. Teggatz
发明人： Dave Baldwin , Sanmukh Patel , Ross E. Teggatz
IPC分类号： G05F1613
CPC分类号： G05F1/613
摘要： The regulator circuit with an auxiliary boundary regulator that provides enhanced transient response includes: an upper comparator 24 having a first input coupled to a feedback node and a second input coupled to a first reference voltage node V_HIGH; a lower comparator 26 having a first input coupled to the feedback node and a second input coupled to a second reference voltage node V_LOW; a first switching device 30 having a control node coupled to an output of the upper comparator 24; a second switching device 28 having a control node coupled to an output of the lower comparator 26; an inductor 36 having a first end coupled to the first and second switching devices 28 and 30, and a second end coupled to an output node Vout; and a feedback circuit 32 and 34 coupled between the output node Vout and the feedback node. This circuit provides a precise, quiet, linear regulator that provides a tightly regulated output with a fast regulator working in parallel to ensure that the output voltage stays within an acceptable boundary.
摘要翻译：具有提供增强的瞬态响应的辅助边界调节器的调节器电路包括：具有耦合到反馈节点的第一输入和耦合到第一参考电压节点V_HIGH的第二输入的上比较器24; 下比较器26具有耦合到反馈节点的第一输入和耦合到第二参考电压节点V_LOW的第二输入; 具有耦合到上比较器24的输出的控制节点的第一开关装置30; 具有耦合到下比较器26的输出的控制节点的第二开关装置28; 电感器36，其具有耦合到第一和第二开关器件28和30的第一端，以及耦合到输出节点Vout的第二端; 以及耦合在输出节点Vout和反馈节点之间的反馈电路32和34。该电路提供了一个精确，安静的线性稳压器，提供紧密调节的输出，并具有并联工作的快速调节器，以确保输出电压保持在可接受的边界内。

82. 发明授权

US5786724A Control of body effect in MOS transistors by switching source-to-body bias 失效
标题翻译：通过切换源极偏置来控制MOS晶体管的体效应
公开(公告)号：US5786724A
公开(公告)日：1998-07-28
申请号：US768876
申请日：1996-12-17
申请人： Ross E. Teggatz
发明人： Ross E. Teggatz
IPC分类号： H03K5/003
CPC分类号： H03K5/003
摘要： A voltage level shifting circuit (FIG. 4) has a plurality of PMOS transistors M.sub.1, M.sub.2, M.sub.3 connected in parallel for respectively driving a capacitive load C.sub.L with a selected different voltage level V.sub.1, V.sub.2 or V.sub.3. Transistors M.sub.1, M.sub.2, M.sub.3 are controlled so that one of them is placed in the ON condition, with the others in the OFF condition, to connect one of the voltages V.sub.1, V.sub.2 or V.sub.3 to charge the load CL. The largest voltage transistor M.sub.3 has its body connected to its source. The lower voltage transistors M.sub.1, M.sub.2 have their bodies respectively connected to switches S.sub.1, S.sub.2, which connect the bodies to the sources when the transistors are placed in the ON condition and connect the bodies to the highest voltage V.sub.3 when the transistors are placed in the OFF condition.
摘要翻译：电压电平移动电路（图4）具有并联连接的多个PMOS晶体管M1，M2，M3，分别驱动具有所选择的不同电压电平V1，V2或V3的电容性负载CL。控制晶体管M1，M2，M3，使其中的一个被置于ON状态，其他的处于OFF状态，以连接电压V1，V2或V3中的一个来对负载CL充电。最大的电压晶体管M3的主体连接到其源极。低电压晶体管M1，M2的主体分别连接到开关S1，S2，开关S1，S2将晶体管置于ON状态时将主体连接到源极，并将晶体管放置在 OFF状态。

83. 发明授权

US5424669A Digitally controlled output slope control/current limit in power integrated circuits 失效
标题翻译：功率集成电路数字控制输出斜率控制/限流
公开(公告)号：US5424669A
公开(公告)日：1995-06-13
申请号：US055071
申请日：1993-04-29
申请人： Ross E. Teggatz , Joe A. Devore
发明人： Ross E. Teggatz , Joe A. Devore
IPC分类号： H03K17/081 , H03K17/16 , H03H11/26
CPC分类号： H03K17/08104 , H03K17/164
摘要： A slope control circuit having a plurality of resistive elements connected in parallel, each of the resistive elements including a control element for causing the associated resistive elements to be one of electrically conductive or electrically nonconductive, a delay circuit having a plurality of delay components coupled together in series, each of the delay components having a predetermined delay, the junction of each different adjacent pair of the delay components being coupled to the control element of a different one of the resistive elements and a load circuit coupled across the plurality of resistive elements. The circuit can further include a delay adjust circuit for adjusting the delay of each of the delay components, either initially or on-line. The resistance of each of the resistive elements can be the same or different. The plurality of resistive elements and the delay components are all disposed on a single semiconductor chip.
摘要翻译：一种具有并联连接的多个电阻元件的斜率控制电路，每个电阻元件包括用于使相关联的电阻元件为导电或不导电的控制元件，具有耦合在一起的多个延迟元件的延迟电路串联地，每个延迟部件具有预定的延迟，每个不同的相邻延迟部件对的结被耦合到不同的电阻元件的控制元件和耦合在多个电阻元件上的负载电路。该电路还可以包括延迟调整电路，用于调整每个延迟部件的延迟，或者是初始的或在线的。每个电阻元件的电阻可以相同或不同。多个电阻元件和延迟元件都设置在单个半导体芯片上。

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