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81. 发明授权

US06361987B1 Gene encoding a protein having asymmetric hydrolase activity for 4-substituted 1,4-dihydropyridine derivatives and its expression product 失效
标题翻译：编码具有4-取代的1,4-二氢吡啶衍生物及其表达产物的不对称水解酶活性的蛋白质的基因
公开(公告)号：US06361987B1
公开(公告)日：2002-03-26
申请号：US09514340
申请日：2000-02-28
申请人： Akira Arisawa , Motoko Matsufuji , Takurou Tsuruta , Kazuyuki Dobashi , Takashi Nakashima , Kunio Isshiki , Takeo Yoshioka
发明人： Akira Arisawa , Motoko Matsufuji , Takurou Tsuruta , Kazuyuki Dobashi , Takashi Nakashima , Kunio Isshiki , Takeo Yoshioka
IPC分类号： C12N914
CPC分类号： C07D211/88 , C07D211/90 , C12N9/18 , C12N9/78 , C12P17/12 , C12P41/006
摘要： This invention provides DNA fragments for efficiently preparing a protein having asymmetric hydrolase activity for 4-substituted 1,4-dihydropyridine derivatives, transformants obtained by using such a DNA fragment, and a process for preparing the aforesaid enzyme. Specifically, an isolated gene derived from the chromosome of Streptomyces viridosporus and encoding a protein having asymmetric hydrolase activity for 4-substituted 1,4-dihydropyridine derivatives, plasmids having the aforesaid gene integrated thereinto, transformants obtained by using such a plasmid, and a process for preparing the aforesaid enzyme by using such a transformant are disclosed. A process for the enzymatic conversion of 4-substituted 1,4-dihydropyridine derivatives by using the aforesaid enzyme is also disclosed.
摘要翻译：本发明提供了用于有效制备对4-取代的1,4-二氢吡啶衍生物具有不对称水解酶活性的蛋白质的DNA片段，以及通过使用这样的DNA片段得到的转化体及其制备方法。具体来说，来源于链球菌链球菌的染色体的分离的基因，编码对4-取代的1,4-二氢吡啶衍生物具有不对称的水解酶活性的蛋白质，将上述基因整合到其中的质粒，使用这样的质粒获得的转化体，公开了通过使用这种转化体制备上述酶的方法。还公开了通过使用上述酶酶促转化4-取代的1,4-二氢吡啶衍生物的方法。

82. 发明授权

US6030951A Chrysomycin derivative compounds and use as antitumor agents 失效
标题翻译：赤霉素衍生物，用作抗肿瘤剂
公开(公告)号：US6030951A
公开(公告)日：2000-02-29
申请号：US308710
申请日：1999-07-08
申请人： Takashi Nakashima , Tadashi Fujii , Kazuya Sakai , Tomohiro Sameshima , Hiroyuki Kumagai , Takeo Yoshioka
发明人： Takashi Nakashima , Tadashi Fujii , Kazuya Sakai , Tomohiro Sameshima , Hiroyuki Kumagai , Takeo Yoshioka
IPC分类号： C07D311/78 , C07D407/04 , C12P17/06 , A61K31/70 , C07H7/04
CPC分类号： C07D407/04 , C07D311/78 , C12P17/06
摘要： Disclosed are the novel C-glycoside compounds Mer-1020dA, Mer-1020dB, Mer-1020dC and Mer-1020dD which have a chromophore group in common with well-known chrysomycins A and B, but can be distinguished from the chrysomycins and the like in that the novel C-glycoside compounds have a sugar residue having a higher degree of oxidation, as well as the compound Mer-1020dE comprising only the chromophore thereof. Among these compounds, the C-glycoside compounds are antibiotics which have low toxicity and can strongly inhibit the growth of solid cancer cells in particular.
摘要翻译： PCT No.PCT / JP97 / 04007 Sec。 371日期：1999年7月8日 102（e）1999年7月8日PCT PCT 1997年11月4日PCT公布。公开号WO98 / 22612 PCT 日期1998年5月28日公开了具有发色团组的新颖的C-糖苷化合物Mer-1020dA，Mer-1020dB，Mer-1020dC和Mer-1020dD，与着名的科莫昔霉素A和B相同，但可以区别于科莫昔霉素因为新型C-糖苷化合物具有较高氧化度的糖残基以及仅包含其发色团的化合物Mer-1020dE。在这些化合物中，C-糖苷化合物是具有低毒性并特别强烈地抑制固体癌细胞生长的抗生素。

83. 发明授权

US5960273A Method of manufacturing a semiconductor device including a bipolar transistor 失效
标题翻译：制造包括双极晶体管的半导体器件的方法
公开(公告)号：US5960273A
公开(公告)日：1999-09-28
申请号：US124507
申请日：1998-07-29
申请人： Takashi Nakashima
发明人： Takashi Nakashima
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/732 , H01L21/8238 , H01L21/22 , H01L21/38
CPC分类号： H01L21/8249 , H01L27/0623 , Y10S257/90
摘要： An improved bipolar transistor of BiCMOS is provided to improve the breakdown voltage between a collector and a base. A low concentration diffusion layer is provided at a main surface of a semiconductor substrate at a boundary between an outer perimeter of an external base layer and an end portion of a field oxide film. The low concentration diffusion layer expands from the main surface of the semiconductor substrate toward the inside of the substrate and has a concentration lower than the impurity concentration of the external base layer.
摘要翻译：提供改进的BiCMOS双极晶体管以提高集电极和基极之间的击穿电压。在半导体衬底的主表面上，在外部基底层的外周和场氧化膜的端部之间的边界处设置低浓度扩散层。低浓度扩散层从半导体衬底的主表面朝向衬底的内部膨胀，并且具有低于外部基底层的杂质浓度的浓度。

84. 发明授权

US5935203A Rectifying transfer gate circuit 失效
标题翻译：整流传输门电路
公开(公告)号：US5935203A
公开(公告)日：1999-08-10
申请号：US18470
申请日：1998-02-04
申请人： Takashi Nakashima
发明人： Takashi Nakashima
IPC分类号： H01L21/8234 , G06F7/50 , G06F7/501 , H01L27/07 , H01L27/088 , H03K17/687 , H03K19/0944 , H03K19/21
CPC分类号： G06F7/501 , H01L27/0727 , H03K19/09441 , H03K19/215 , G06F2207/3876
摘要： A rectifying transfer gate circuit includes first and second field effect transistors and one diode. The source of the first field effect transistor is coupled to a first input node and the gate thereof is coupled to a second input node. Meanwhile, the source of the second field effect transistor is coupled to the second input node and the gate thereof is coupled to the first input node. The diode is coupled between the common drain of the first and second field effect transistors and an output node, so as to increase the speed of the operation in the application circuit utilizing the above rectifying transfer gate circuit.
摘要翻译：整流传输门电路包括第一和第二场效应晶体管和一个二极管。第一场效应晶体管的源极耦合到第一输入节点，并且其栅极耦合到第二输入节点。同时，第二场效应晶体管的源极耦合到第二输入节点，并且其栅极耦合到第一输入节点。二极管耦合在第一和第二场效应晶体管的公共漏极和输出节点之间，以便利用上述整流传输门电路来增加应用电路中的操作速度。

85. 发明授权

US5661086A Process for manufacturing a plurality of strip lead frame semiconductor devices 失效
标题翻译：用于制造多个带状引线框半导体器件的工艺
公开(公告)号：US5661086A
公开(公告)日：1997-08-26
申请号：US584299
申请日：1996-01-11
申请人： Takashi Nakashima , Keiji Takai , Kouji Tateishi
发明人： Takashi Nakashima , Keiji Takai , Kouji Tateishi
IPC分类号： H01L21/48 , H01L23/13 , H01L23/31 , H01L23/498 , H01L21/52 , H01L21/58 , H01L21/60
CPC分类号： H01L23/49811 , H01L21/4803 , H01L21/4846 , H01L23/13 , H01L23/3128 , H01L2224/45144 , H01L2224/48091 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/07802 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , Y10T29/49121
摘要： Method for producing semiconductor devices comprises a first step in which a plurality of metal substrates each of which is provided with a die mounting region at a central portion thereof are connected in series to produce a train of connected metal substrates by means of first connecting tabs and a pair of first side rails each of which is provided with first positioning pilot apertures are connected to the train by means of second connecting tabs to produce a metal substrate frame, a second step in which a plurality of circuit substrates each of which is provided with a lead pattern around an opening formed at the central portion thereof are connected in series by means of third connecting tabs to produce a train of connected circuit substrates and a pair of second side rails each of which is provided with second positioning pilot apertures are connected by fourth connecting tabs to produce a circuit substrate frame, a third step in which both frames are alinged with each other making use of the first and second positioning pilot apertures and are adhered with each other to produce a die mounting substrate frame, and a fourth step in which a semiconductor die is received in a cavity defined by the die mounting region and the opening of each die mounting substrate and solder balls are connected to terminal pads which form one ends of the lead pattern while pads of the semiconductor die are connected to wire bonding pads which form other ends of the lead pattern, and connecting tabs are removed so as to produce separate semiconductor devices.
摘要翻译：用于制造半导体器件的方法包括：第一步骤，其中在其中心部分设置有管芯安装区域的多个金属基板串联连接，以通过第一连接突片和一对第一侧轨，每个第一侧轨设置有第一定位导向孔，通过第二连接翼连接到列上，以产生金属基底框架;第二步，其中多个电路基板设置有围绕其中心部分形成的开口周围的引线图案通过第三连接突片串联连接，以产生一系列连接的电路基板和一对第二侧轨，每个第二侧轨设置有第二定位导向孔，第四连接片以产生电路衬底框架，第三步骤，其中两个框架彼此相互嵌合使用第一和第二定位导向孔并彼此粘合以产生模具安装基板框架，以及第四步骤，其中半导体管芯被容纳在由管芯安装区域和每个管芯的开口限定的空腔中安装基板和焊球连接到形成引线图案的一端的端子焊盘，而半导体管芯的焊盘连接到形成引线图案的另一端的引线接合焊盘，并且连接接线片被移除以产生单独的半导体设备。

86. 发明授权

US5640047A Ball grid assembly type semiconductor device having a heat diffusion function and an electric and magnetic shielding function 失效
标题翻译：具有热扩散功能和电磁屏蔽功能的球栅组装型半导体器件
公开(公告)号：US5640047A
公开(公告)日：1997-06-17
申请号：US641351
申请日：1996-04-30
申请人： Takashi Nakashima
发明人： Takashi Nakashima
IPC分类号： H01L23/12 , H01L23/367 , H01L23/498 , H01L23/552 , H01L23/58 , H05K3/00 , H05K3/34 , H05K3/40 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/49816 , H01L23/3677 , H01L23/552 , H01L23/585 , H01L2224/32013 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/73265 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H05K3/0094 , H05K3/3478 , H05K3/4069
摘要： A semiconductor device comprises a circuit substrate being provided with a first lead pattern and a second lead pattern on a front surface and rear surface thereof respectively. The first lead pattern includes a die mounting region and conductive leads. The second lead pattern includes first outer connecting terminal lands connected with the die mounting region by way of first vias, second outer connecting terminal lands connected with the conductive leads of the first lead pattern by way of second vias, and a ground plane connected with the first outer connecting terminal lands while being electrically and magnetically shielded from the second outer connecting terminal lands. Solder balls are mounted on the first and second outer connecting terminal lands respectively. A semiconductor die is fixedly mounted on the die mounting region. Bonding wires connect electrode pads mounted on the semiconductor die with the conductive leads respectively. A resin package seals the semiconductor die and the bonding wires on the front surface of the circuit substrate. The semiconductor device effectively restricts the occurrence of cross talk noises caused by parasitic current on the conductive layer, improves heat diffusion of the semiconductor device and effectively prevents malfunctions of semiconductor devices caused by electromagnetic noises.
摘要翻译：一种半导体器件包括分别在其前表面和后表面上设置有第一引线图案和第二引线图案的电路基板。第一引线图案包括管芯安装区域和导电引线。第二引线图案包括通过第一通孔与管芯安装区域连接的第一外部连接端子焊盘，通过第二通孔与第一引线图案的导电引线连接的第二外部连接端子焊盘以及与第二引线图形连接的接地平面第一外部连接端子平台，同时与第二外部连接端子台面电磁屏蔽。焊球分别安装在第一和第二外部连接端子台上。半导体管芯固定地安装在管芯安装区域上。接合线分别将安装在半导体管芯上的电极焊盘与导电引线连接起来。树脂封装件密封半导体管芯和电路基板前表面上的接合线。半导体器件有效地限制了由导电层上的寄生电流引起的串扰噪声的发生，改善了半导体器件的热扩散，并有效地防止了由电磁噪声引起的半导体器件的故障。

87. 发明授权

US5542841A Burner apparatus for use in a glass furnace 失效
标题翻译：用于玻璃熔炉的燃烧器
公开(公告)号：US5542841A
公开(公告)日：1996-08-06
申请号：US317583
申请日：1994-10-03
申请人： Takashi Nakashima , Masanobu Kodera
发明人： Takashi Nakashima , Masanobu Kodera
IPC分类号： C03B5/235 , F23C5/02 , F23D14/78 , F23M5/02 , F23D11/36
CPC分类号： C03B5/2353 , F23C5/02 , F23D14/78 , F23M5/025 , Y02P40/55
摘要： A burner apparatus is used in a glass furnace incorporating a plurality of pairs of burners, each pair of burners being provided at the diametrically opposite locations of the furnace and operated alternately. The burner apparatus comprises a water cooled wall located in an opening of a burner tile, a cooling water supply device for supplying cooling water to the backside surface of the water cooled wall, and an opening formed in the water cooled wall. The forward end portion of a fuel injection nozzle provided on the forward end of the burner is fitted in the opening formed in the water cooled wall.
摘要翻译：燃烧器装置用于包含多对燃烧器的玻璃炉中，每对燃烧器设置在炉的径向相对的位置，交替地操作。燃烧器装置包括位于燃烧器瓦片的开口中的水冷壁，用于向水冷壁的后侧表面供给冷却水的冷却水供应装置和形成在水冷壁中的开口。设置在燃烧器前端上的燃料喷射喷嘴的前端部装配在形成于水冷壁上的开口中。

88. 发明授权

US5415481A Feeding of ink ribbon based on shapes of a plurality of previously printed characters 失效
标题翻译：基于多个先前打印的字符的形状进行墨带的供给
公开(公告)号：US5415481A
公开(公告)日：1995-05-16
申请号：US184595
申请日：1994-01-21
申请人： Takashi Nakashima , Ichiro Nakamura
发明人： Takashi Nakashima , Ichiro Nakamura
IPC分类号： B41J33/36 , B41J33/54
CPC分类号： B41J33/36 , B41J33/54
摘要： A traveling amount calculating unit calculates a minimum traveling amount of a printing transfer material required for a plurality of shapes printed previously not overlying a shape to be printed next on the printing transfer material. Based on the traveling amount, a traveling unit travels the printing transfer material. Then, a transfer unit transfers a shape to be printed next.
摘要翻译：移动量计算单元计算在打印转印材料上以前未打印下一个打印形状的多个形状所需的打印转印材料的最小行进量。基于移动量，移动单元行进打印转印材料。然后，转印单元转印接下来要印刷的形状。

89. 发明授权

US5394397A Shared buffer memory type ATM communication system and method with a broadcast facility 失效
标题翻译：共享缓冲存储器类型ATM通信系统和方法与广播设施
公开(公告)号：US5394397A
公开(公告)日：1995-02-28
申请号：US38615
申请日：1993-03-29
申请人： Junichirou Yanagi , Yoshihiro Ashi , Takahiko Kozaki , Akihiko Takase , Takashi Nakashima
发明人： Junichirou Yanagi , Yoshihiro Ashi , Takahiko Kozaki , Akihiko Takase , Takashi Nakashima
IPC分类号： H04M3/42 , H04L12/18 , H04L12/761 , H04L12/931 , H04L12/951 , H04Q3/52 , H04Q11/04 , H04L12/56 , H04J3/26 , H04L12/48
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/203 , H04L49/309
摘要： An ATM switching system which includes an input interface which is provided every incoming line and serves to convert header information of each input cell into internal routing information, a shared buffer memory and a cell writing control unit which forms normal cell list structures, which are prepared in correspondence to outgoing lines and in which a plurality of normal cells are chained together with their next addresses, and a broadcast cell list structure, in which a plurality of broadcast cells are chained together with their next addresses, in the shared buffer memory, and serves to add successively the input cells to ones of the list structures, which are selected in correspondence to respective internal routing information. The invention also includes a cell reading control unit which serves to fetch selectively the cell from the list structures formed in the shared buffer memory to distribute the cell thus fetched to the associated outgoing lines. The cell reading control unit includes a broadcast destination table for "storing broadcast destination specifying information for specifying the outgoing lines, through which the broadcast cell is to be output, using a bit pattern, in correspondence to the internal routing information of the broadcast cell".
摘要翻译：一种ATM交换系统，其包括为每条输入线路提供的输入接口，用于将每个输入单元的头信息转换为内部路由信息，共享缓冲存储器和形成正常小区列表结构的小区写入控制单元，其被准备对应于输出线，并且其中多个正常小区与其下一个地址一起链接在一起，以及广播小区列表结构，其中多个广播小区与其下一个地址一起连接在共享缓冲存储器中，以及用于将输入单元连续地添加到与各个内部路由信息相对应地选择的列表结构中的一个。本发明还包括一个单元读取控制单元，用于从形成在共享缓冲存储器中的列表结构中选择性地提取单元，以将由此提取的单元分配到相关联的输出行。小区读取控制单元包括：广播目的地表，用于根据广播小区的内部路由信息，使用位模式存储用于指定要输出广播小区的出行的广播目的地指定信息; 。

90. 发明授权

US5351213A Integrated semiconductor memory device utilizing a test circuit 失效
标题翻译：利用测试电路的集成半导体存储器件
公开(公告)号：US5351213A
公开(公告)日：1994-09-27
申请号：US843260
申请日：1992-02-28
申请人： Takashi Nakashima
发明人： Takashi Nakashima
IPC分类号： G01R31/28 , G11C17/00 , G11C29/00 , G11C29/04 , G11C29/12 , G11C29/34 , G11C29/38 , G11C29/56 , H01L21/66 , H01L27/10 , G11C13/00
CPC分类号： G11C29/12 , G11C29/04 , G11C29/38 , H01L2924/0002
摘要： A semiconductor memory device of the type having a test circuit incorporated integrally therewith generates test data to be batch written into the device's memory cells. The memory device includes at least one memory block to which there may be connected sense amplifiers through which read/write operations can be effected. A test circuit is also provided which function is to test each memory block. A peripheral circuit is formed electrically connected to any memory blocks. Accordingly, memory blocks as well as the peripheral circuit are formed on a semiconductor substrate onto which there is formed a `single` layer having both high (undoped thin poly-Si current paths-108CH) and low (doped thin poly-Si joint path-108SD) resistivity regions therein. The inherent properties of the undoped high-resistivity current paths 108 CH are such that in response to control signals from control gate electrodes, an electrical conductance of the current paths can be altered. The resultant structure yields improvements in manufacturing costs, test time and ancillary costs associated with memory block testing.
摘要翻译：具有整体结合的测试电路的类型的半导体存储器件产生批量写入器件的存储单元的测试数据。存储器件包括至少一个存储器块，可以通过该存储器块连接读出放大器，通过该读出放大器可以实现读/写操作。还提供了测试电路，其功能是测试每个存储器块。外围电路形成为电连接到任何存储器块。因此，存储块以及外围电路形成在半导体衬底上，在半导体衬底上形成具有高（未掺杂的多晶硅半导体电极108CH）和低掺杂的薄多晶硅结合路径的“单”层 -108SD）电阻率区域。未掺杂的高电阻率电流路径108CH的固有特性使得响应于来自控制栅电极的控制信号，可以改变电流路径的电导。所得到的结构产生了与记忆块测试相关的制造成本，测试时间和辅助成本的改进。

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