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81. 发明申请

US20080171426A1 UNIAXIAL STRAIN RELAXATION OF BIAXIAL-STRAINED THIN FILMS USING ION IMPLANTATION 失效
标题翻译：使用离子植入的双应变薄膜的单轴应变松弛
公开(公告)号：US20080171426A1
公开(公告)日：2008-07-17
申请号：US11622524
申请日：2007-01-12
申请人： Zhibin Ren , Katherine L. Saenger , Haizhou Yin
发明人： Zhibin Ren , Katherine L. Saenger , Haizhou Yin
IPC分类号： H01L21/425
CPC分类号： H01L21/26506 , H01L21/823807 , H01L29/78 , H01L29/7848 , Y10S438/938
摘要： A method for achieving uniaxial strain on originally biaxial-strained thin films after uniaxial strain relaxation induced by ion implantation is provided. The biaxial-strained thin film receives ion implantation after being covered by a patterned implant block structure. The strain in the uncovered region is relaxed by ion implantation, which induces the lateral strain relaxation in the covered region. When the implant block structure is narrow (dimension is comparable to the film thickness), the original biaxial strain will relax uniaxially in the lateral direction.
摘要翻译：提供了一种通过离子注入诱发的单轴应变松弛之后在原始双轴应变薄膜上实现单轴应变的方法。双轴应变薄膜在被图案化的植入物块结构覆盖之后接收离子注入。未覆盖区域的应变通过离子注入而松弛，这引起覆盖区域的横向应变弛豫。当植入物块结构窄（尺寸与膜厚度相当）时，原始双轴应变将在横向方向上单轴弛豫。

82. 发明授权

US07256670B2 Diaphragm activated micro-electromechanical switch 有权
标题翻译：隔膜激活微机电开关
公开(公告)号：US07256670B2
公开(公告)日：2007-08-14
申请号：US10523310
申请日：2002-08-26
申请人： Christopher V. Jahnes , Jennifer L. Lund , Katherine L. Saenger , Richard P. Volant
发明人： Christopher V. Jahnes , Jennifer L. Lund , Katherine L. Saenger , Richard P. Volant
IPC分类号： H01H51/22
CPC分类号： H01H59/0009
摘要： A micro-electromechanical (MEM) RF switch provided with a deflectable membrane (60) activates a switch contact or plunger (40). The membrane incorporates interdigitated metal electrodes (70) which cause a stress gradient in the membrane when activated by way of a DC electric field. The stress gradient results in a predictable bending or displacement of the membrane (60), and is used to mechanically displace the switch contact (30). An RF gap area (25) located within the cavity (250) is totally segregated from the gaps (71) between the interdigitated metal electrodes (70). The membrane is electrostatically displaced in two opposing directions, thereby aiding to activate and deactivate the switch. The micro-electromechanical switch includes: a cavity (250); at least one conductive path (20) integral to a first surface bordering the cavity; a flexible membrane (60) parallel to the first surface bordering the cavity (250), the flexible membrane (60) having a plurality of actuating electrodes (70); and a plunger (40) attached to the flexible membrane (60) in a direction away from the actuating electrodes (70), the plunger (40) having a conductive surface that makes electric contact with the conductive paths, opening and closing the switch.
摘要翻译：设置有可偏转膜（60）的微机电（MEM）RF开关激活开关触点或柱塞（40）。膜包含交叉指向的金属电极（70），其通过DC电场激活时引起膜中的应力梯度。应力梯度导致膜（60）的可预测的弯曲或位移，并且用于机械地移动开关触点（30）。位于空腔（250）内的RF间隙区域（25）与交叉指向的金属电极（70）之间的间隙（71）完全分离。膜在两个相反的方向上静电位移，从而有助于启动和停用开关。微机电开关包括：空腔（250）; 至少一个导电通路（20），与所述空腔相邻的第一表面成一体; 柔性膜（60），其平行于与所述腔（250）接壤的所述第一表面，所述柔性膜（60）具有多个致动电极（70）; 以及沿远离所述致动电极（70）的方向附接到所述柔性膜（60）的柱塞（40），所述柱塞（40）具有导电表面，所述导电表面与所述导电路径电接触，所述开关闭合。

83. 发明授权

US06187679B1 Low temperature formation of low resistivity titanium silicide 失效
标题翻译：低电阻率硅化钛的低温形成
公开(公告)号：US06187679B1
公开(公告)日：2001-02-13
申请号：US08807739
申请日：1997-02-26
申请人： Cyril Cabral, Jr. , Lawrence Alfred Clevenger , Francois Max d'Heurle , James McKell Edwin Harper , Randy William Mann , Glen Lester Miles , James Spiros Nakos , Ronnen Andrew Roy , Katherine L. Saenger
发明人： Cyril Cabral, Jr. , Lawrence Alfred Clevenger , Francois Max d'Heurle , James McKell Edwin Harper , Randy William Mann , Glen Lester Miles , James Spiros Nakos , Ronnen Andrew Roy , Katherine L. Saenger
IPC分类号： H01L2144
CPC分类号： C30B1/02 , C30B29/10 , H01L21/28518 , H01L29/665
摘要： Low resistivity titanium silicide, and semiconductor devices incorporating the same, may be formed by titanium alloy comprising titanium and 1-20 atomic percent refractory metal deposited in a layer overlying a silicon substrate, the substrate is then heated to a temperature sufficient to substantially form C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, and more preferably is Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900° C., and more preferably between about 600-700° C.
摘要翻译：低电阻率钛硅化物和包含该低电阻率钛硅化物的半导体器件可以由在钛硅衬底上沉积的钛和1-20原子百分比的难熔金属的钛合金形成，然后将衬底加热至足以基本形成C54 相钛硅化物。钛合金还可以包含硅，难熔金属可以是Mo，W，Ta，Nb，V或Cr，更优选是Ta或Nb。用于形成低电阻率硅化钛的加热步骤在低于900℃的温度下进行，更优选在约600-700℃之间

84. 发明授权

US5828131A Low temperature formation of low resistivity titanium silicide 失效
标题翻译：低电阻率硅化钛的低温形成
公开(公告)号：US5828131A
公开(公告)日：1998-10-27
申请号：US586046
申请日：1996-01-16
申请人： Cyril Cabral, Jr. , Lawrence Alfred Clevenger , Francois Max d'Heurle , James McKell Edwin Harper , Randy William Mann , Glen Lester Miles , James Spiros Nakos , Ronnen Andrew Roy , Katherine L. Saenger
发明人： Cyril Cabral, Jr. , Lawrence Alfred Clevenger , Francois Max d'Heurle , James McKell Edwin Harper , Randy William Mann , Glen Lester Miles , James Spiros Nakos , Ronnen Andrew Roy , Katherine L. Saenger
IPC分类号： C23C20/02 , C30B1/02 , H01L21/28 , H01L21/285 , H01L21/336 , H01L29/45
CPC分类号： C30B1/02 , C30B29/10 , H01L21/28518 , H01L29/665
摘要： Low resistivity titanium silicide, and semiconductor devices incorporating the same, may be formed by titanium alloy comprising titanium and 1-20 atomic percent refractory metal deposited in a layer overlying a silicon substrate, the substrate is then heated to a temperature sufficient to substantially form C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, and more preferably is Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900.degree. C., and more preferably between about 600.degree.-700.degree. C.
摘要翻译：低电阻率钛硅化物和包含该低电阻率钛硅化物的半导体器件可以由在钛硅衬底上沉积的钛和1-20原子百分比的难熔金属的钛合金形成，然后将衬底加热至足以基本形成C54 相钛硅化物。钛合金还可以包含硅，难熔金属可以是Mo，W，Ta，Nb，V或Cr，更优选是Ta或Nb。用于形成低电阻率硅化钛的加热步骤在低于900℃的温度下进行，更优选在约600℃至700℃之间。

85. 发明授权

US5585998A Isolated sidewall capacitor with dual dielectric 失效
标题翻译：隔离侧壁电容器，双电介质
公开(公告)号：US5585998A
公开(公告)日：1996-12-17
申请号：US577166
申请日：1995-12-22
申请人： David E. Kotecki , William H. Ma , Katherine L. Saenger
发明人： David E. Kotecki , William H. Ma , Katherine L. Saenger
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/115 , H01G4/06 , H01G4/008 , H01G7/00
CPC分类号： H01L27/11502 , H01L27/10852 , H01L28/55 , Y10T29/435
摘要： An isolated sidewall capacitor with dual dielectric, which includes two capacitors. The first capacitor includes a first conductor on top of a substrate, a first non-conductor on top of and substantially in register with the first conductor, the first conductor and first non-conductor having a first opening formed therein, a non-conductive sidewall spacer formed in the first opening, the non-conductive sidewall spacer having a second opening formed therein, and a second conductor formed in the second opening. The second capacitor includes the second conductor, a first non-conductor disposed over the top portion of the second conductor, a third conductor disposed over the first non-conductor, and the third conductor electrically connected to the first conductor. A second non-conductor isolates the first conductor from the second conductor.
摘要翻译：具有双电介质的隔离侧壁电容器，其包括两个电容器。所述第一电容器包括位于衬底顶部的第一导体，位于所述第一导体顶部并基本上与所述第一导体对准的第一非导体，所述第一导体和第一非导体具有形成在其中的第一开口，非导电侧壁在第一开口中形成的间隔件，其中形成有第二开口的非导电侧壁隔离件和形成在第二开口中的第二导体。第二电容器包括第二导体，设置在第二导体的顶部上的第一非导体，设置在第一非导体上的第三导体，以及电连接到第一导体的第三导体。第二非导体将第一导体与第二导体隔离。

86. 发明申请

US20110086473A1 HYBRID ORIENTATION SEMICONDUCTOR STRUCTURE WITH REDUCED BOUNDARY DEFECTS AND METHOD OF FORMING SAME 有权
标题翻译：具有减少边界缺陷的混合方向半导体结构及其形成方法
公开(公告)号：US20110086473A1
公开(公告)日：2011-04-14
申请号：US12972771
申请日：2010-12-20
申请人： Haizhou Yin , John A. Ott , Katherine L. Saenger , Chun-Yung Sung
发明人： Haizhou Yin , John A. Ott , Katherine L. Saenger , Chun-Yung Sung
IPC分类号： H01L21/8238 , H01L21/265
CPC分类号： H01L21/02694 , H01L21/02532 , H01L21/76264 , Y10S438/973
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for forming hybrid orientation substrates and semiconductor device structures. A direct-silicon-bonded (DSB) silicon layer having a (011) surface crystal orientation is bonded to a base silicon substrate having a (001) surface crystal orientation to form a DSB wafer in which the in-plane direction of the (011) DSB layer is aligned with an in-plane direction of the (001) base substrate. Selected regions of the DSB layer are amorphized down to the base substrate to form amorphized regions aligned with the mutually orthogonal in-plane directions of the (001) base substrate, followed by recrystallization using the base substrate as a template. This optimal arrangement of DSB layer, base substrate, and amorphized region orientation provides a near-vertical, essentially defect-free boundary between original-orientation and changed-orientation silicon regions, thus enabling complete boundary region removal with smaller footprint shallow trench isolation than possible with ATR methods not so optimized.
摘要翻译：本发明提供用于形成混合取向基板和半导体器件结构的改进的非晶化/模板重结晶（ATR）方法。具有（011）表面晶体取向的直接硅键合（DSB）硅层被结合到具有（001）表面晶体取向的基底硅基板上，以形成其中面内<110>方向的DSB晶片（011）DSB层与（001）基底的面内<110>方向对准。 DSB层的选定区域被非晶化到底部基板以形成与（001）基底基板的相互正交的平面内100°方向对准的非晶形区域，然后使用基底基板作为模板进行重结晶。 DSB层，基底和非晶区域取向的这种最佳布置提供了原始取向和改变取向硅区域之间近似垂直的，基本上无缺陷的边界，因此可以实现完整的边界区域移除，并且可以实现更小的占地面积的浅沟槽隔离 ATR方法没有如此优化。

87. 发明授权

US07785939B2 Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers 失效
标题翻译：具有通过层叠模板层的局部非晶化和重结晶形成的所选半导体晶体取向的平面基板
公开(公告)号：US07785939B2
公开(公告)日：2010-08-31
申请号：US11566579
申请日：2006-12-04
申请人： Joel P. de Souza , John A. Ott , Alexander Reznicek , Katherine L. Saenger
发明人： Joel P. de Souza , John A. Ott , Alexander Reznicek , Katherine L. Saenger
IPC分类号： H01L21/00
CPC分类号： H01L21/02667 , H01L21/02609 , H01L21/2022 , H01L21/76251 , H01L21/76275 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/1054 , H01L29/66772 , H01L29/78654 , H01L29/78696
摘要： A method utilizing localized amorphization and recrystallization of stacked template layers is provided for making a planar substrate having semiconductor layers of different crystallographic orientations. Also provided are hybrid-orientation semiconductor substrate structures built with the methods of the invention, as well as such structures integrated with various CMOS circuits comprising at least two semiconductor devices disposed on different surface orientations for enhanced device performance.
摘要翻译：提供了利用层叠模板层的局部非晶化和重结晶的方法，用于制造具有不同晶体取向的半导体层的平面基板。还提供了利用本发明的方法构建的混合取向半导体衬底结构，以及与各种CMOS电路集成的这种结构，其包括设置在不同表面取向上的至少两个半导体器件，用于增强器件性能。

88. 发明申请

US20100044758A1 CMOS WITH CHANNEL P-FINFET AND CHANNEL N-FINFET HAVING DIFFERENT CRYSTALLINE ORIENTATIONS AND PARALLEL FINS 有权
标题翻译：具有通道的具有不同晶体结构和并联FINS的通道P-FINFET和通道N-FinFET的CMOS
公开(公告)号：US20100044758A1
公开(公告)日：2010-02-25
申请号：US12197459
申请日：2008-08-25
申请人： GUY M. COHEN , Katherine L. Saenger
发明人： GUY M. COHEN , Katherine L. Saenger
IPC分类号： H01L29/04 , H01L21/84 , G06F19/00
CPC分类号： H01L27/0924 , H01L21/34 , H01L21/845 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/045 , H01L29/66795 , H01L29/785
摘要： An integrated circuit is fabricated with at least one p-FinFET device and at least one n-FinFET device situated parallel to each other. A first silicon layer having a first crystalline orientation is bonded to a second silicon layer having a second crystalline orientation. The first and second orientations are different from each other. A volume of material is formed that extends through the first layer from the second layer up to the surface of the first layer. The material has a crystalline orientation that substantially matches the orientation of the second layer. Areas of the surface of the first layer that are outside of the region are selectively etched to create a first plurality of fins and areas inside the region to create a second plurality of fins. The etching leaves the first and second pluralities of fins parallel to each other with different surface crystal orientations.
摘要翻译：制造具有至少一个p-FinFET器件和至少一个彼此平行的n-FinFET器件的集成电路。具有第一晶体取向的第一硅层被结合到具有第二晶体取向的第二硅层上。第一和第二取向彼此不同。形成一定体积的材料，其从第二层延伸穿过第一层直到第一层的表面。该材料具有基本上与第二层的取向一致的晶体取向。选择性地蚀刻在区域外部的第一层的表面的区域，以在该区域内产生第一多个散热片和区域，以产生第二多个散热片。蚀刻使得第一和第二多个翅片彼此平行但具有不同的表面晶体取向。

89. 发明申请

US20080248626A1 SHALLOW TRENCH ISOLATION SELF-ALIGNED TO TEMPLATED RECRYSTALLIZATION BOUNDARY 审中-公开
标题翻译： SHOWOW TRENCH ISOLATION自对准至模拟重构边界
公开(公告)号：US20080248626A1
公开(公告)日：2008-10-09
申请号：US11697102
申请日：2007-04-05
申请人： Yaocheng Liu , Zhijiong Luo , Katherine L. Saenger , Chun-Yung Sung , Rajasekhar Venigalla , Haizhou Yin
发明人： Yaocheng Liu , Zhijiong Luo , Katherine L. Saenger , Chun-Yung Sung , Rajasekhar Venigalla , Haizhou Yin
IPC分类号： H01L21/762
CPC分类号： H01L21/26506 , H01L21/02667 , H01L21/187 , H01L21/76224
摘要： A hybrid orientation direct-semiconductor-bond (DSB) substrate with shallow trench isolation (STI) that is self-aligned to recrystallization boundaries is formed by patterning a hard mask layer for STI, a first amorphization implantation into openings in the hard mask layer, lithographic patterning of portions of a top semiconductor layer, a second amorphization implantation into exposed portions of the DSB substrate, recrystallization of the portions of the top semiconductor layer, and formation of STI utilizing the pattern in the hard mask layer. The edges of patterned photoresist for the second amorphization implantation are located within the openings in the patterned hard mask layer. Defective boundary regions formed underneath the openings in the hard mask layer are removed during the formation of STI to provide a leakage path free substrate. Due to elimination of a requirement for increased STI width, device density is increased compared to non-self-aligning process integration schemes.
摘要翻译：通过将STI的硬掩模层图案化，在硬掩模层的开口中进行第一非晶化注入，形成具有与重结晶边界自对准的浅沟槽隔离（STI）的混合取向直接半导体结合（DSB）顶部半导体层的部分的平版印刷图案化，第二非晶化注入到DSB衬底的暴露部分中，顶部半导体层的部分的再结晶，以及利用硬掩模层中的图案形成STI。用于第二非晶化注入的图案化光致抗蚀剂的边缘位于图案化的硬掩模层的开口内。在形成STI期间去除在硬掩模层中形成在开口下面的有缺陷的边界区域，以提供无泄漏路径的衬底。由于消除了对于增加的STI宽度的要求，与非自对准工艺集成方案相比，器件密度增加。

90. 发明申请

US20080142894A1 GATE STACK ENGINEERING BY ELECTROCHEMICAL PROCESSING UTILIZING THROUGH-GATE-DIELECTRIC CURRENT FLOW 有权
标题翻译：通过电化学处理利用栅极电介质电流流动的栅极堆叠工程
公开(公告)号：US20080142894A1
公开(公告)日：2008-06-19
申请号：US12040350
申请日：2008-02-29
申请人： Philippe M. Vereecken , Veeraraghavan S. Basker , Cyril Cabral , Emanuel I. Cooper , Hariklia Deligianni , Martin M. Frank , Rajarao Jammy , Vamsi Krishna Paruchuri , Katherine L. Saenger , Xiaoyan Shao
发明人： Philippe M. Vereecken , Veeraraghavan S. Basker , Cyril Cabral , Emanuel I. Cooper , Hariklia Deligianni , Martin M. Frank , Rajarao Jammy , Vamsi Krishna Paruchuri , Katherine L. Saenger , Xiaoyan Shao
IPC分类号： H01L27/088 , H01L29/423
CPC分类号： H01L21/2885 , C25D3/50 , C25D5/02 , C25D5/024 , C25D5/54 , C25D7/123 , C25D9/04 , C25F3/14 , H01L21/28079 , H01L21/28114 , H01L21/76885 , H01L29/513 , H01L29/517 , H01L29/78648
摘要： A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.
摘要翻译：提供了一种用于将栅极金属或其它导电或半导体材料直接电镀在诸如栅极电介质的电介质上的方法。该方法包括选择衬底，电介质层和电解质溶液或熔体，其中衬底，电介质层和电解质溶液或熔体的组合允许电化学电流从衬底通过电介质层进入电解质溶液或熔化。还提供了利用电介质电流流动的电介质电化学修饰方法。

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