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81. 发明授权

US5349248A Adaptive programming method for antifuse technology 失效
标题翻译：反熔丝技术的自适应编程方法
公开(公告)号：US5349248A
公开(公告)日：1994-09-20
申请号：US940125
申请日：1992-09-03
申请人： David B. Parlour , F. Erich Goetting , Stephen M. Trimberger
发明人： David B. Parlour , F. Erich Goetting , Stephen M. Trimberger
IPC分类号： G11C17/16 , H03K19/177 , H01H37/76
CPC分类号： H03K19/17704 , G11C17/16
摘要： For antifuse programmable integrated circuit devices, in particular FPGA devices, the invention allows for alternative routing around antifuses which fail to program. The chip architecture includes wiring segments and antifuses which together allow for alternative routes around every antifuse in the event of failure of that antifuse. The method includes programming the device under control of a computer which can recalculate routes in the event of an antifuse which fails to program. Preferably the initial routing distributes unused wiring segments through the chip to be available for routing around a failed antifuse. When a failure occurs, the method includes determining an alternative route around every failed antifuse. The alternative route may be established directly after the antifuse has failed or after all initially selected antifuses have been programmed. The method also includes swapping of logic cell inputs, logic cells, and/or logic blocks from their original layout to adapt to a failed antifuse without changing the timing of signals which would have used the failed antifuse.
摘要翻译：对于反熔丝可编程集成电路器件，特别是FPGA器件，本发明允许在不能编程的反熔丝周围的替代路由。芯片架构包括布线段和反熔丝，这些连接段和反熔丝一起允许在反熔丝发生故障的情况下围绕每个反熔丝的替代路线。该方法包括在计算机的控制下对设备进行编程，该计算机可以在无法编程的反熔丝的情况下重新计算路由。优选地，初始路由分配通过芯片的未使用的接线段以可用于围绕故障反熔丝进行布线。当发生故障时，该方法包括确定围绕每个故障反熔丝的替代路线。替代路线可以在反熔丝失败之后直接建立，或者在所有初始选择的反熔丝已被编程之后。该方法还包括从其原始布局交换逻辑单元输入，逻辑单元和/或逻辑块以适应故障反熔丝而不改变将使用故障反熔丝的信号的定时。

82. 发明授权

US5224056A Logic placement using positionally asymmetrical partitioning algorithm 失效
标题翻译：使用位置不对称分割算法的逻辑放置
公开(公告)号：US5224056A
公开(公告)日：1993-06-29
申请号：US784844
申请日：1991-10-30
申请人： Mon R. Chene , Stephen M. Trimberger
发明人： Mon R. Chene , Stephen M. Trimberger
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A modified partitioning method for placement of a circuit design into a programmable integrated circuit device (PICD), the PICD having a specific distribution of physical resources corresponding to a specific circuit structure. The circuit design includes a plurality of circuit elements which include specific circuit elements which correspond to the specific circuit structure. The modified method includes the steps of identifying the specific circuit elements and partitioning the plurality of circuit elements such that the identified specific circuit elements are placed in a location corresponding to the specific physical distribution of resources. In one embodiment of the modified partitioning method according to the present invention, the step of partitioning further includes the steps of forming into a cell the identified specific circuit elements and performing a first phase of partitioning wherein the cell and the remaining ones of the plurality of circuit elements are partitioned into successively smaller groups until a stop condition is satisfied. The cell is then decomposed such that the contents of the group containing the cell change to include the specific circuit elements. The group containing the specific circuit elements is then partitioned such that the area and the location of the group corresponds to the specific physical distribution of resources.
摘要翻译：一种用于将电路设计放置到可编程集成电路器件（PICD）中的修改的分割方法，PICD具有与特定电路结构对应的物理资源的特定分布。电路设计包括多个电路元件，其包括对应于特定电路结构的特定电路元件。修改的方法包括以下步骤：识别特定电路元件并分割多个电路元件，使得所识别的特定电路元件被放置在与特定的资源物理分布对应的位置。在根据本发明的修改分割方法的一个实施例中，分割步骤还包括以下步骤：将识别的特定电路元件形成单元格并执行第一分区阶段，其中单元和多个电路元件被分成相继较小的组，直到满足停止条件。然后分解单元，使得包含单元的组的内容改变以包括特定的电路元件。然后对包含特定电路元件的组进行分区，使得组的区域和位置对应于资源的特定物理分布。

83. 发明授权

US08832462B2 Protecting against differential power analysis attacks on sensitive data 有权
标题翻译：保护敏感数据的差分功率分析攻击
公开(公告)号：US08832462B2
公开(公告)日：2014-09-09
申请号：US12877968
申请日：2010-09-08
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： G06F11/30 , G06F12/14 , G06F11/00
CPC分类号： G06F21/755
摘要： An embodiment of a method is disclosed for protecting sensitive data from discovery during an operation performed on input data with the sensitive data. This embodiment of the method includes performing the operation on a first quantity of random data with the sensitive data using a circuit arrangement before performing the operation with the sensitive data on the input data using the circuit arrangement. After performing the operation with the sensitive data on the first quantity of the random data, the operation is performed with the sensitive data on the input data using the circuit arrangement. After performing the operation with the sensitive data on the input data, the operation is performed with the sensitive data on a second quantity of random data using the circuit arrangement.
摘要翻译：公开了一种方法的实施例，用于在对具有敏感数据的输入数据执行的操作期间保护敏感数据免于发现。该方法的该实施例包括使用电路装置在利用敏感数据对输入数据进行操作之前利用敏感数据对第一数量的随机数据进行操作。在使用随机数据的第一数量的敏感数据执行操作之后，使用电路装置对输入数据的敏感数据进行操作。在使用输入数据的敏感数据执行操作之后，使用电路装置对敏感数据执行第二数量的随机数据。

84. 发明授权

US08418006B1 Protecting a design for an integrated circuit using a unique identifier 有权
标题翻译：使用唯一标识符保护集成电路的设计
公开(公告)号：US08418006B1
公开(公告)日：2013-04-09
申请号：US12961770
申请日：2010-12-07
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： G01R31/28
CPC分类号： G06F21/10 , G06F17/5045 , G06F21/73 , G09C1/00 , H04L9/0866 , H04L9/3278 , H04L2209/12
摘要： An embodiment of the invention relates to an integrated circuit that includes an identifier reader which may be, e.g., a physically unclonable function reader that generates a unique and reproducible identifier for the integrated circuit, and a related method. An error correction code may be employed to correct an error in the value of the reproducible identifier. Values of signals in the integrated circuit are selectively inverted dependent on values of the reproducible identifier, and an error corrector uses the values of the reproducible identifier to restore the values of the signals. The signals may be produced as outputs of look-up tables that selectively invert the values of the signals dependent on the value of the reproducible identifier. The signals may be inputs to the integrated circuit, internal signals, outputs, or state data. A test may validate a state of the integrated circuit and disable operation if the test fails.
摘要翻译：本发明的实施例涉及一种集成电路，其包括标识符读取器，其可以是例如物理上不可克隆的功能读取器，其生成用于集成电路的唯一且可再现的标识符以及相关方法。可以采用纠错码来校正可再现标识符的值中的错误。集成电路中的信号的值根据可重现标识符的值有选择地反向，并且误差校正器使用可再现标识符的值来恢复信号的值。信号可以被产生为查找表的输出，其选择性地反转取决于可再现标识符的值的信号的值。信号可以是集成电路，内部信号，输出或状态数据的输入。测试可以验证集成电路的状态，如果测试失败，则禁用操作。

85. 发明授权

US08415976B1 Optimized interconnection networks 有权
标题翻译：优化互联网络
公开(公告)号：US08415976B1
公开(公告)日：2013-04-09
申请号：US13323169
申请日：2011-12-12
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： H01L25/00
CPC分类号： H03K19/17736
摘要： A non-blocking routing network includes a plurality of external inputs and external outputs. Each row of a first plurality of routing rows provides a routing path from at least one of the external inputs to at least one of the external outputs and includes first through fourth multiplexers. Each row of a second plurality of routing rows provides a routing path from at least two of the external inputs to at least two of the external outputs. Each routing row of the second plurality of routing rows contains at least one less multiplexer relative to a routing row of the first plurality of routing rows, the one less multiplexer corresponding to at least two external inputs or two external outputs that are logically equivalent to one another.
摘要翻译：非阻塞路由网络包括多个外部输入和外部输出。第一多个路由行的每一行提供从至少一个外部输入到至少一个外部输出的路由路径，并且包括第一至第四多路复用器。第二多个路由行中的每一行提供从至少两个外部输入到外部输出中的至少两个的路由路径。第二多个路由行的每个路由行包含相对于第一多个路由行中的路由行的至少一个多路复用器，该多路复用器对应于至少两个外部输入或两个逻辑上等同于一个的外部输出另一个。

86. 发明授权

US08183881B1 Configuration memory as buffer memory for an integrated circuit 有权
标题翻译：配置存储器作为集成电路的缓冲存储器
公开(公告)号：US08183881B1
公开(公告)日：2012-05-22
申请号：US10813414
申请日：2004-03-29
申请人： Benjamin J. Stassart , Stephen M. Trimberger
发明人： Benjamin J. Stassart , Stephen M. Trimberger
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/177
摘要： Method and apparatus for using configuration memory for buffer memory is described. Drivers associated with a portion of the configuration memory are rendered incapable of creating a contentious state irrespective of information stored the portion of configuration memory. Configuration data is received in a non-configuration data format and buffered in the portion of the configuration memory.
摘要翻译：描述了使用配置存储器用于缓冲存储器的方法和装置。与配置存储器的一部分相关联的驱动器被赋予不能创建有争议的状态，而与存储配置存储器的该部分的信息无关。配置数据以非配置数据格式接收并缓存在配置存储器的部分中。

87. 发明授权

US07853799B1 Microcontroller-configurable programmable device with downloadable decryption 有权
标题翻译：微控制器可配置可编程器件，具有可下载的解密功能
公开(公告)号：US07853799B1
公开(公告)日：2010-12-14
申请号：US10877900
申请日：2004-06-24
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： G06F11/30
CPC分类号： G06F21/76
摘要： A programmable encryption approach involves the use of a downloadable decryptor. According to an example embodiment of the present invention, an FPGA device includes a microcontroller for configuring logic circuitry on the FPGA device. A memory register is implemented for storing encryption key data and a message authentication code (MAC). When the FPGA device is to be configured using a configuration bitstream, a MAC is calculated for a decryptor and sent to the microcontroller along with an encryption key. The microcontroller stores the encryption key and MAC in a register to which access is limited. When the decryptor is downloaded to the microprocessor, a MAC is calculated on the downloaded decryptor and compared with the stored MAC. If the calculated MAC matches the stored MAC, the decryptor is allowed to access the key.
摘要翻译：可编程加密方法涉及使用可下载解密器。根据本发明的示例实施例，FPGA器件包括用于配置FPGA器件上的逻辑电路的微控制器。实现存储器寄存器用于存储加密密钥数据和消息认证码（MAC）。当使用配置比特流来配置FPGA器件时，为解密器计算MAC并将其与加密密钥一起发送到微控制器。微控制器将加密密钥和MAC存储在访问受限的寄存器中。当将解密器下载到微处理器时，在下载的解密器上计算MAC并与存储的MAC进行比较。如果所计算的MAC与存储的MAC匹配，则解密器被允许访问该密钥。

88. 发明授权

US07701057B1 Semiconductor device having structures for reducing substrate noise coupled from through die vias 有权
标题翻译：半导体器件具有用于减少从通孔中耦合的衬底噪声的结构
公开(公告)号：US07701057B1
公开(公告)日：2010-04-20
申请号：US11796101
申请日：2007-04-25
申请人： Arifur Rahman , Stephen M. Trimberger
发明人： Arifur Rahman , Stephen M. Trimberger
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L23/481 , H01L23/552 , H01L23/585 , H01L25/0657 , H01L2224/0554 , H01L2224/05573 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05671 , H01L2224/05678 , H01L2224/0568 , H01L2224/05681 , H01L2224/05684 , H01L2224/13025 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2924/3011 , H01L2924/013 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor device having structures for reducing substrate noise coupled from through die vias (TDVs) is described. In one example, a semiconductor device has a substrate, at least one signal through die via (TDV), and ground TDVs. The substrate includes conductive interconnect formed on an active side thereof. The conductive interconnect includes ground conductors and digital signal conductors. Each signal TDV is formed in the substrate and is electrically coupled to at least one of the digital signal conductors. The ground TDVs are formed in the substrate in a ring around the at least one signal TDV. The ground TDVs are electrically coupled to the ground conductors. The ground TDVs provide a sink for noise coupled into the substrate from the signal TDVs. In this manner, the ground TDVs mitigate noise coupled to noise-sensitive components formed on the substrate.
摘要翻译：描述了具有用于减少从通孔（TDV）耦合的衬底噪声的结构的半导体器件。在一个示例中，半导体器件具有衬底，至少一个通过管芯通孔（TDV）的信号和接地TDV。基板包括形成在其活性侧上的导电互连。导电互连包括接地导体和数字信号导体。每个信号TDV形成在衬底中并且电耦合到至少一个数字信号导体。接地TDV以围绕至少一个信号TDV的环形成在衬底中。接地TDV电耦合到接地导体。接地TDV为信号TDV提供耦合到衬底中的噪声接收器。以这种方式，接地TDV减轻耦合到在衬底上形成的噪声敏感部件的噪声。

89. 发明授权

US07605458B1 Method and apparatus for integrating capacitors in stacked integrated circuits 有权
标题翻译：集成电路集成电容器的方法和装置
公开(公告)号：US07605458B1
公开(公告)日：2009-10-20
申请号：US11701807
申请日：2007-02-01
申请人： Arifur Rahman , Stephen M. Trimberger
发明人： Arifur Rahman , Stephen M. Trimberger
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L23/642 , H01L2224/05001 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05181 , H01L2224/05184 , H01L2224/05568 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05671 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2924/15311 , H01L2924/19015 , H01L2924/19103 , H01L2924/00014
摘要： Method and apparatus for integrating capacitors in stacked integrated circuits are described. One aspect of the invention relates to a semiconductor assembly having a carrier substrate, a plurality of integrated circuit dice, and at least one metal-insulator-metal (MIM) capacitor. The integrated circuit dice are vertically stacked on the carrier substrate. Each MIM capacitor is disposed between a first integrated circuit die and a second integrated circuit die of the plurality of integrated circuit dice. The at least one MIM capacitor is fabricated on at least one of a face of the first integrated circuit die and a backside of the second integrated circuit die.
摘要翻译：描述了在堆叠集成电路中集成电容器的方法和装置。本发明的一个方面涉及一种具有载体衬底，多个集成电路芯片和至少一种金属 - 绝缘体 - 金属（MIM）电容器的半导体组件。集成电路芯片垂直堆叠在载体基板上。每个MIM电容器设置在多个集成电路芯片的第一集成电路管芯和第二集成电路管芯之间。所述至少一个MIM电容器被制造在所述第一集成电路管芯的表面和所述第二集成电路管芯的背面中的至少一个上。

90. 发明授权

US07523380B1 Methods and structures for providing programmable width and error correction in memory arrays in programmable logic devices 有权
标题翻译：用于在可编程逻辑器件中的存储器阵列中提供可编程宽度和误差校正的方法和结构
公开(公告)号：US07523380B1
公开(公告)日：2009-04-21
申请号：US11590329
申请日：2006-10-31
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： G11C29/00
CPC分类号： G11C11/4125 , G06F11/1044 , G11C2029/0409 , H03K19/1776 , H03K19/17764
摘要： A random access memory (RAM) in a programmable logic device (PLD) supports error correction as well as a configurable data width. The number of bits in a user data word varies by the selected configuration of the RAM, while the number of bits in the error correction code (ECC) is unvarying, and is based on the total width of the memory. In some embodiments, separate ports are provided for the user data and the ECC data. Thus, ECC data can be written to an ECC portion of the RAM array at a given RAM address, while at the same time user data is written to or read from a configurable user data portion of the RAM array at the same RAM address. In other embodiments, a single memory access port is used for both user data and ECC data.
摘要翻译：可编程逻辑器件（PLD）中的随机存取存储器（RAM）支持错误校正以及可配置的数据宽度。用户数据字中的位数随着所选择的RAM的配置而变化，而纠错码（ECC）中的位数是不变的，并且基于存储器的总宽度。在一些实施例中，为用户数据和ECC数据提供单独的端口。因此，ECC数据可以以给定的RAM地址被写入到RAM阵列的ECC部分，同时用户数据被写入或从RAM阵列的可配置用户数据部分读取在相同的RAM地址。在其他实施例中，单个存储器访问端口用于用户数据和ECC数据。

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