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81. 发明申请

US20120054422A1 Wide Input/Output Memory with Low Density, Low Latency and High Density, High Latency Blocks 有权
标题翻译：宽输入/输出存储器，具有低密度，低延迟和高密度，高延迟模块
公开(公告)号：US20120054422A1
公开(公告)日：2012-03-01
申请号：US12862094
申请日：2010-08-24
申请人： Shiqun Gu , Matthew M. Nowak , Anand Srinivasan
发明人： Shiqun Gu , Matthew M. Nowak , Anand Srinivasan
IPC分类号： G06F12/06 , G06F12/08
CPC分类号： G11C11/4076 , H01L23/481 , H01L24/73 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/00012 , H01L2924/00
摘要： External memory having a high density, high latency memory block; and a low density, low latency memory block. The two memory blocks may be separately accessed by one or more processing functional units. The access may be a direct memory access, or by way of a bus or fabric switch. Through-die vias may connect the external memory to a die comprising the one or more processing functional units.
摘要翻译：具有高密度，高延迟的存储器块的外部存储器; 和低密度，低延迟的存储器块。两个存储器块可以被一个或多个处理功能单元单独访问。访问可以是直接存储器访问，或者通过总线或结构交换机。通孔通孔可以将外部存储器连接到包括一个或多个处理功能单元的管芯。

82. 发明申请

US20120025362A1 Reinforced Wafer-Level Molding to Reduce Warpage 审中-公开
标题翻译：加强晶圆级成型以减少翘曲
公开(公告)号：US20120025362A1
公开(公告)日：2012-02-02
申请号：US12846910
申请日：2010-07-30
申请人： Arvind Chandrasekaran , Shiqun Gu , Zhongping Bao
发明人： Arvind Chandrasekaran , Shiqun Gu , Zhongping Bao
IPC分类号： H01L21/50 , H01L21/56 , H01L23/28
CPC分类号： H01L21/565 , H01L21/568 , H01L21/6836 , H01L23/3121 , H01L23/562 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/73 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L2221/68327 , H01L2221/6834 , H01L2224/14181 , H01L2224/16145 , H01L2224/16221 , H01L2224/73204 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/10253 , H01L2924/15311 , H01L2924/181 , H01L2924/3511 , H01L2224/81 , H01L2224/11 , H01L2924/00
摘要： A method for forming an electrical package to reduce warpage. The method includes providing a wafer and coupling a die thereto. A mold compound material is applied to the wafer such that the mold compound material surrounds the die. The method further includes applying a reinforcing material to the mold compound material. The mold compound material is thereby disposed between the wafer and the reinforcing material.
摘要翻译：一种用于形成电气封装以减少翘曲的方法。该方法包括提供晶片并将模具耦合到其上。将模具复合材料施加到晶片上，使得模具复合材料围绕模具。该方法还包括将增强材料施加到模具复合材料。因此，模具复合材料设置在晶片和增强材料之间。

83. 发明申请

US20120012998A1 Conductive Sidewall for Microbumps 有权
标题翻译：导电侧壁为Microbumps
公开(公告)号：US20120012998A1
公开(公告)日：2012-01-19
申请号：US12837717
申请日：2010-07-16
申请人： Arvind Chandrasekaran , Shiqun Gu , Christine S. Hay-Riege
发明人： Arvind Chandrasekaran , Shiqun Gu , Christine S. Hay-Riege
IPC分类号： H01L23/498 , H01L21/60 , H01L21/768
CPC分类号： H01L24/81 , H01L21/76877 , H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/742 , H01L25/0657 , H01L25/50 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/0361 , H01L2224/0401 , H01L2224/051 , H01L2224/05567 , H01L2224/056 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11472 , H01L2224/1161 , H01L2224/11849 , H01L2224/119 , H01L2224/13017 , H01L2224/13018 , H01L2224/13021 , H01L2224/13023 , H01L2224/13076 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/16058 , H01L2224/16148 , H01L2224/81193 , H01L2224/81203 , H01L2224/81815 , H01L2225/06513 , H01L2924/00013 , H01L2924/00014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3841 , H01L2224/13099 , H01L2224/05552 , H01L2924/00
摘要： Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.
摘要翻译：微型接头中的电迁移会导致微胶囊中的空隙，从而降低了包含微型电池的集成电路的使用寿命。通过在焊料周围形成铜壳，可能会在微胶囊中增加电迁移寿命。一个微型块的铜壳接触第二个微型块的铜壳，以封闭微型接头的焊料。铜壳允许通过微型块的更高的电流密度。因此，可以以更小的间距制造较小的微胶片，而不会发生电迁移的故障。此外，铜壳减少了衬底上的微型接头之间的短路或桥接。

84. 发明授权

US08067816B2 Techniques for placement of active and passive devices within a chip 有权
标题翻译：有源和无源器件放置在芯片内的技术
公开(公告)号：US08067816B2
公开(公告)日：2011-11-29
申请号：US12364844
申请日：2009-02-03
申请人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Matthew Nowak
发明人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Matthew Nowak
IPC分类号： H01L29/00
CPC分类号： H01L27/0617 , H01L23/481 , H01L23/5223 , H01L23/5227 , H01L27/0688 , H01L28/10 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).
摘要翻译：半导体管芯包括具有第一和第二侧面的半导体衬底层，与半导体衬底层的第二侧相邻的金属层，在半导体衬底层的第一侧上的有源层中的一个或多个有源器件; 以及与有源层电连通的金属层中的无源器件。无源器件可以通过硅通孔（TSV）电耦合到有源层。

85. 发明授权

US07939926B2 Via first plus via last technique for IC interconnects 有权
标题翻译：通过第一个加上通过IC互连的最后技术
公开(公告)号：US07939926B2
公开(公告)日：2011-05-10
申请号：US12334433
申请日：2008-12-12
申请人： Kenneth Kaskoun , Shiqun Gu , Bart Swinnen
发明人： Kenneth Kaskoun , Shiqun Gu , Bart Swinnen
IPC分类号： H01L23/02
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/06181 , H01L2924/0002 , H01L2924/00
摘要： A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are coupled together. The first set of vias are physically smaller than the second set of vias. The first set of vias are produced prior to circuitry on the die, and the second set of vias are produced after circuitry on the die. A second die having a set of interconnects is stacked relative to the first die in which the interconnects couple to the first set of vias.
摘要翻译：多层IC器件包含第一裸片，其包括具有第一组和第二组通孔的衬底。第一组通孔从衬底的一侧延伸，并且第二组通孔从衬底的相对侧延伸。两组通孔耦合在一起。第一组通孔在物理上小于第二组通孔。第一组通孔在芯片上的电路之前产生，并且第二组通孔在芯片上的电路之后产生。具有一组互连件的第二管芯相对于第一管芯堆叠，其中互连件耦合到第一组通孔。

86. 发明申请

US20110101347A1 Interconnect Sensor for Detecting Delamination 失效
标题翻译：用于检测分层的互连传感器
公开(公告)号：US20110101347A1
公开(公告)日：2011-05-05
申请号：US12613444
申请日：2009-11-05
申请人： Brian Matthew Henderson , Shiqun Gu , Homyar C. Mogul , Mark M. Nakamoto , Arvind Chandrasekaran
发明人： Brian Matthew Henderson , Shiqun Gu , Homyar C. Mogul , Mark M. Nakamoto , Arvind Chandrasekaran
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L22/34 , G01N3/066 , G01N2203/0096
摘要： An interconnect sensor for detecting delamination due to coefficient of thermal expansion mismatch and/or mechanical stress. The sensor comprises a conductive path that includes a via disposed between two back end of line metal layers separated by a dielectric. The via is coupled between a first probe structure and a second probe structure and mechanically coupled to a stress inducing structure. The via is configured to alter the conductive path in response to mechanical stress caused by the stress inducing structure. The stress inducing structure can be a through silicon via or a solder ball. The dielectric material can be a low-k dielectric material. In another embodiment, a method of forming an interconnect sensor is provided for detecting delamination.
摘要翻译：用于检测由于热膨胀失配系数和/或机械应力引起的分层的互连传感器。该传感器包括导电路径，该导电路径包括通过电介质隔开的线金属层的两个后端之间的通孔。通孔耦合在第一探针结构和第二探针结构之间，并机械耦合到应力诱导结构。通孔配置成响应于由应力诱导结构引起的机械应力而改变导电路径。应力诱导结构可以是硅通孔或焊球。介电材料可以是低k电介质材料。在另一个实施例中，提供形成互连传感器的方法用于检测分层。

87. 发明申请

US20100193905A1 Techniques for Placement of Active and Passive Devices Within a Chip 有权
标题翻译：芯片内主动和被动设备放置技术
公开(公告)号：US20100193905A1
公开(公告)日：2010-08-05
申请号：US12364844
申请日：2009-02-03
申请人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Matthew Nowak
发明人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Matthew Nowak
IPC分类号： H01L27/08 , H01L21/98
CPC分类号： H01L27/0617 , H01L23/481 , H01L23/5223 , H01L23/5227 , H01L27/0688 , H01L28/10 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).
摘要翻译：半导体管芯包括具有第一和第二侧面的半导体衬底层，与半导体衬底层的第二侧相邻的金属层，在半导体衬底层的第一侧上的有源层中的一个或多个有源器件; 以及与有源层电连通的金属层中的无源器件。无源器件可以通过硅通孔（TSV）电耦合到有源层。

88. 发明申请

US20100075460A1 Low Cost Die-To-Wafer Alignment/Bond For 3d IC Stacking 有权
标题翻译：低成本芯片对晶片对齐/贴合3d IC堆叠
公开(公告)号：US20100075460A1
公开(公告)日：2010-03-25
申请号：US12236967
申请日：2008-09-24
申请人： Shiqun Gu , Thomas R. Toms
发明人： Shiqun Gu , Thomas R. Toms
IPC分类号： H01L21/00
CPC分类号： H01L23/544 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2223/54406 , H01L2223/54426 , H01L2223/5446 , H01L2223/5448 , H01L2225/06513 , H01L2225/06593 , H01L2924/0002 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： The cost associated with alignment in a stacked IC device can be reduced by aligning multiple die instead of a single die during the alignment step. In one embodiment, the alignment structures are placed in the scribe line instead of within the die itself. Aligning four die instead of one eliminates the need for as many alignment indicators and thus more silicon on the wafer can be used for active areas. In addition, this method allows for yield improvement through binning of dies having the same yield configuration.
摘要翻译：在对准步骤期间，可以通过对准多个管芯而不是单个管芯来降低与叠置的IC器件中的对准相关的成本。在一个实施例中，对准结构被放置在划线中，而不是在模具本身内。对准四个模具而不是一个消除了对于多个对准指示器的需要，因此在晶片上更多的硅可用于有源区域。此外，该方法允许通过对具有相同产量构型的模具进行分级来提高产量。

89. 发明申请

US20100045630A1 Capacitive MEMS-Based Display with Touch Position Sensing 审中-公开
标题翻译：具有触摸位置检测功能的电容式MEMS基显示器
公开(公告)号：US20100045630A1
公开(公告)日：2010-02-25
申请号：US12194412
申请日：2008-08-19
申请人： Shiqun Gu , Matthew Nowak
发明人： Shiqun Gu , Matthew Nowak
IPC分类号： G06F3/045
CPC分类号： G06F3/0412 , G06F3/044
摘要： A micro-electro-mechanical systems (MEMS) pixel for display and touch position sensing includes a substrate and a capacitive element. The capacitive element includes one or more pixels having a first conductive platelet above the substrate, and a second conductive platelet above and spaced apart from the first conductive platelet, the two platelets forming the capacitive element. A connection to each platelet provides for applying a voltage, wherein the platelet separation changes according to the applied voltage. A transparent dielectric plate, spaced apart from and positioned opposite the substrate, covers the at least one pixel. A capacitance sensing circuit attached to the connection to each platelet of the pixel senses changes in capacitance not resulting from the applied voltage.
摘要翻译：用于显示和触摸位置感测的微电子机械系统（MEMS）像素包括基板和电容元件。电容元件包括一个或多个像素，其具有在衬底上方的第一导电片，以及在第一导电片上方并与第一导电片形成间隔开的第二导电片，所述两片片形成电容元件。与每个血小板的连接提供施加电压，其中血小板分离根据所施加的电压而改变。与衬底间隔开并与衬底相对设置的透明电介质板覆盖至少一个像素。附接到与像素的每个血小板的连接的电容感测电路感测不是由施加电压引起的电容变化。

90. 发明申请

US20090327983A1 Predictive Modeling of Interconnect Modules for Advanced On-Chip Interconnect Technology 失效
标题翻译：用于高级片上互连技术的互连模块的预测建模
公开(公告)号：US20090327983A1
公开(公告)日：2009-12-31
申请号：US12474297
申请日：2009-05-29
申请人： Xia Li , Wei Zhao , Yu Cao , Shiqun Gu , Seung H. Kang , Matthew Nowak
发明人： Xia Li , Wei Zhao , Yu Cao , Shiqun Gu , Seung H. Kang , Matthew Nowak
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A computer program product estimates performance of an interconnect structure of a semiconductor integrated circuit (IC). The program product includes code executing on a computer to calculate at least one electrical characteristic of the interconnect structure based on input data accounting for multiple layers of the interconnect structure. The electrical characteristics can be capacitance, resistance, and/or inductance. The capacitance may be based upon multiple components, including a fringe capacitance component, a terminal capacitance component, and a coupling capacitance component.
摘要翻译：计算机程序产品估计半导体集成电路（IC）的互连结构的性能。程序产品包括在计算机上执行的代码，用于基于考虑到互连结构的多层的输入数据来计算互连结构的至少一个电特性。电气特性可以是电容，电阻和/或电感。电容可以基于多个分量，包括边缘电容分量，端子电容分量和耦合电容分量。

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