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81. 发明授权

US06479098B1 Method to solve particle performance of FSG layer by using UFU season film for FSG process 有权
标题翻译：通过使用UFU季膜对FSG过程解决FSG层的粒子性能的方法
公开(公告)号：US06479098B1
公开(公告)日：2002-11-12
申请号：US09747135
申请日：2000-12-26
申请人： Ming-Hwa Yoo , Yi-Lung Cheng , Szu-An Wu , Ying-Lang Wang
发明人： Ming-Hwa Yoo , Yi-Lung Cheng , Szu-An Wu , Ying-Lang Wang
IPC分类号： C23C1640
CPC分类号： H01J37/32477 , C23C16/4404 , Y10T428/2495 , Y10T428/265
摘要： A method for reducing contaminants in a processing chamber 10 having chamber plasma processing region components comprising the following steps. The chamber plasma processing region components are cleaned. The chamber is then seasoned as follows. A first USG layer is formed over the chamber plasma processing region components. An FSG layer is formed over the first USG layer. A second USG layer is formed over the FSG layer. Wherein the USG, FSG, and second USG layers comprise a UFU season film. A UFU season film coating the chamber plasma processing region components of a processing chamber comprises: an inner USG layer over the chamber plasma processing region components; an FSG layer over the inner USG layer; and an outer USG layer over the FSG layer.
摘要翻译：一种用于减少具有室等离子体处理区域部件的处理室10中的污染物的方法，包括以下步骤。腔室等离子体处理区域部件被清洁。然后如下调节室。在室等离子体处理区域部件上形成第一USG层。在第一USG层上形成FSG层。在FSG层上形成第二个USG层。其中USG，FSG和第二USG层包括UFU季电影。 UFU季涂膜处理室的室等离子体处理区域部件包括：室上的内部USG层等离子体处理区域部件; 内部USG层上的FSG层; 以及FSG层上的外部USG层。

82. 发明授权

US06436791B1 Method of manufacturing a very deep STI (shallow trench isolation) 有权
标题翻译：制造非常深的STI（浅沟槽隔离）的方法
公开(公告)号：US06436791B1
公开(公告)日：2002-08-20
申请号：US09880259
申请日：2001-06-14
申请人： Shih-Chi Lin , Szu-An Wu , Ying-Lang Wang , Guey-Bao Huang
发明人： Shih-Chi Lin , Szu-An Wu , Ying-Lang Wang , Guey-Bao Huang
IPC分类号： H01L21302
CPC分类号： H01L21/76224
摘要： A method of forming a shallow trench isolation structure comprising the following steps. A substrate having an upper surface is provided. A pad oxide layer is formed upon the substrate. A nitride layer is formed over the pad oxide layer. The nitride layer having an upper surface. A trench is formed by etching the nitride layer, pad oxide layer and a portion of the substrate. The trench having a bottom and side walls. An oxide film is deposited upon the etched nitride layer surface, and the bottom and side walls of trench. The oxide film is removed from over the etched nitride layer surface, and the bottom of the trench to expose a portion of substrate within the trench. The removal of oxide film leaving oxide spacers over the trench side walls. Epitaxial silicon is selectively deposited over the exposed portion of substrate, filling the trench. A thermal oxide layer is formed over the epitaxial silicon, annealing the interface between the epitaxial silicon and the oxide spacers. The etched nitride layer and the oxide layer from over the etched substrate; and a portion of the oxide spacers extending above the surface of the etched substrate are removed, whereby the shallow trench isolation structure is formed within the trench.
摘要翻译：一种形成浅沟槽隔离结构的方法，包括以下步骤。提供具有上表面的基板。衬底氧化层形成在衬底上。在衬垫氧化物层上形成氮化物层。氮化物层具有上表面。通过蚀刻氮化物层，衬垫氧化物层和衬底的一部分来形成沟槽。沟槽具有底部和侧壁。在蚀刻的氮化物层表面和沟槽的底部和侧壁上沉积氧化物膜。从蚀刻的氮化物层表面上方的氧化膜和沟槽的底部去除氧化膜，以露出沟槽内的衬底的一部分。去除在沟槽侧壁上留下氧化物间隔物的氧化物膜。外延硅被选择性地沉积在衬底的暴露部分上，填充沟槽。在外延硅上形成热氧化层，退火外延硅与氧化物间隔物之间的界面。蚀刻的氮化物层和来自蚀刻的衬底上的氧化物层; 并且去除在蚀刻的衬底的表面上方延伸的氧化物间隔物的一部分，由此在沟槽内形成浅沟槽隔离结构。

83. 发明授权

US06399522B1 PE-silane oxide particle performance improvement 失效
标题翻译： PE-硅烷氧化物颗粒性能改善
公开(公告)号：US06399522B1
公开(公告)日：2002-06-04
申请号：US09075115
申请日：1998-05-11
申请人： Chun-Ching Tsan , Hung-Ju Chien , Chun-Chang Chen , Ying-Lang Wang
发明人： Chun-Ching Tsan , Hung-Ju Chien , Chun-Chang Chen , Ying-Lang Wang
IPC分类号： H01L2131
CPC分类号： H01L21/02164 , C23C16/02 , C23C16/402 , H01L21/02211 , H01L21/02274 , H01L21/02312 , H01L21/31612
摘要： A method of forming a PE-silane oxide layer with a greatly reduced particle count is described. A semiconductor substrate is provided over which a silicon oxide film is to be formed. The silicon oxide film is formed by the steps of: 1) pre-flowing a non-silane gas into a deposition chamber for at least two seconds whereby the pre-flowing step prevents formation of particles on the silicon oxide film, and 2) thereafter depositing a silicon oxide film by chemical vapor deposition by flowing a silane gas into the deposition chamber to complete formation of a silicon oxide film using plasma-enhanced chemical vapor deposition in the fabrication of an integrated circuit.
摘要翻译：描述了形成具有大大降低的粒子数的PE-硅烷氧化物层的方法。提供半导体衬底，在其上形成氧化硅膜。氧化硅膜是通过以下步骤形成的：1）将非硅烷气体预先流入沉积室至少两秒钟，由此预流步骤防止在氧化硅膜上形成颗粒，2）之后通过将硅烷气体流入沉积室中，通过化学气相沉积来沉积氧化硅膜，以在集成电路的制造中使用等离子体增强化学气相沉积来形成氧化硅膜。

84. 发明授权

US06395635B1 Reduction of tungsten damascene residue 有权
标题翻译：还原钨镶嵌残渣
公开(公告)号：US06395635B1
公开(公告)日：2002-05-28
申请号：US09206741
申请日：1998-12-07
申请人： Ying-Lang Wang , Jowei Dun
发明人： Ying-Lang Wang , Jowei Dun
IPC分类号： H01L21302
CPC分类号： H01L21/31053 , H01L21/3212
摘要： A CMP process is provided for the reduction of tungsten damascene residue and the elimination of surface scratch within the surface that is being polished. A three step polishing procedure of the ILD is followed by a two step buffing procedure of the ILD. The three step polishing procedure reduces the device defect count by eliminating damascene residue from the polished surface. The two step buffing procedure reduces micro scratch within the polished surface thus improving device throughput. A two step buffing procedure is applied to the IMD. Oxide buffing is applied and consists of a three step polishing procedure followed by a two step buffing procedure.
摘要翻译：提供了一种CMP工艺，用于减少钨镶嵌残余物并消除正在抛光的表面内的表面划痕。 ILD的三步抛光程序之后是ILD的两步抛光程序。三步抛光程序通过从抛光表面去除镶嵌残留物来减少设备缺陷计数。两步抛光程序减少抛光表面内的微刮痕，从而提高设备的生产能力。对IMD应用两步抛光程序。应用氧化物抛光，并由三步抛光程序组成，其后是两步抛光程序。

85. 发明授权

US06323141B1 Method for forming anti-reflective coating layer with enhanced film thickness uniformity 有权
标题翻译：用于形成具有增强的膜厚均匀性的抗反射涂层的方法
公开(公告)号：US06323141B1
公开(公告)日：2001-11-27
申请号：US09541485
申请日：2000-04-03
申请人： Szu-Au Wu , Chun-Ching Tsan , Wen-Kung Cheng , Ying-Lang Wang
发明人： Szu-Au Wu , Chun-Ching Tsan , Wen-Kung Cheng , Ying-Lang Wang
IPC分类号： H01L2131
CPC分类号： H01L21/3145 , C23C16/24 , C23C16/402 , H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/0276 , H01L21/28123 , H01L21/31612 , H01L21/32137 , H01L21/32139
摘要： A method for forming a patterned reflective layer first employs a substrate. There is then formed over the substrate a blanket reflective layer. There is then formed upon the blanket reflective layer an anti-reflective coating (ARC) layer formed employing a plasma enhanced chemical vapor deposition (PECVD) method employing a deposition gas composition comprising silane, nitrous oxide and argon. There is then formed upon the blanket anti-reflective coating (ARC) layer a blanket photoresist layer. There is then photoexposed and developed the blanket photoresist layer to form a patterned photoresist layer. There is then etched, while employing a first etch method, the blanket anti-reflective coating (ARC) layer to form a patterned anti-reflective coating (ARC) layer while employing the patterned photoresist layer as a first etch mask layer. Finally, there is then etched, while employing a second etch method, the blanket reflective layer to form the patterned reflective layer while employing at least the patterned anti-reflective coating (ARC) layer as a second etch mask layer.
摘要翻译：用于形成图案化反射层的方法首先采用基板。然后在衬底上形成覆盖层反射层。然后在毯反射层上形成使用采用包含硅烷，一氧化二氮和氩的沉积气体组合物的等离子体增强化学气相沉积（PECVD）方法形成的抗反射涂层（ARC）层。然后在橡皮布抗反射涂层（ARC）层上形成覆盖光致抗蚀剂层。然后，将曝光的光刻胶照射并显影，以形成图案化的光致抗蚀剂层。然后，在采用第一蚀刻方法的情况下，使用覆盖层抗反射涂层（ARC）层，同时使用图案化的光致抗蚀剂层作为第一蚀刻掩模层，来形成图案化的抗反射涂层（ARC）层。最后，在采用第二蚀刻方法的同时，使用至少图案化的抗反射涂层（ARC）层作为第二蚀刻掩模层，同时使用第二蚀刻方法来蚀刻，以形成图案化的反射层。

86. 发明授权

US06232043B1 Rule to determine CMP polish time 有权
标题翻译：确定CMP抛光时间的规则
公开(公告)号：US06232043B1
公开(公告)日：2001-05-15
申请号：US09318471
申请日：1999-05-25
申请人： Hway-Chi Lin , Yu-Ku Lin , Wen-Pin Chang , Ying-Lang Wang
发明人： Hway-Chi Lin , Yu-Ku Lin , Wen-Pin Chang , Ying-Lang Wang
IPC分类号： G03F700
CPC分类号： B24B37/013 , B24B37/042 , B24B49/12 , H01L21/31053 , H01L21/76224
摘要： A simple method for calculating the optimum amount of HDP deposited material that needs to be removed during CMP (without introducing dishing) is described. This method derives from our observation of a linear relationship between the amount of material that needs to be removed in order to achieve full planarization and a quantity called “OD for CMP density”. The latter is defined as PA×(100−PS) where PA is the percentage of active area relative to the total wafer area and PS is the percentage of sub-areas relative to the total wafer area. The sub-areas are regions in the dielectric, above the active areas, that are etched out prior to CMP. Thus, once the materials have been characterized, the optimum CMP removal thickness is readily calculated for a wide range of different circuit implementations.
摘要翻译：描述了一种用于计算在CMP期间需要去除的HDP沉积材料的最佳量的简单方法（不引入凹陷）。该方法来源于我们观察到需要去除的材料的量之间的线性关系以实现完全平坦化，并且称为“用于CMP密度的OD”。后者被定义为PAx（100-PS），其中PA是相对于总晶片面积的有效面积的百分比，PS是相对于总晶片面积的子区域的百分比。子区域是在CMP之前被蚀刻出的有源区域之上的电介质区域。因此，一旦材料被表征，就可以很容易地计算各种不同电路实现的最佳CMP去除厚度。

87. 发明授权

US07470584B2 TEOS deposition method 有权
标题翻译： TEOS沉积法
公开(公告)号：US07470584B2
公开(公告)日：2008-12-30
申请号：US11040307
申请日：2005-01-21
申请人： Yi-Lung Cheng , Hong-Jui Chang , Ying-Lang Wang
发明人： Yi-Lung Cheng , Hong-Jui Chang , Ying-Lang Wang
IPC分类号： H01L21/31 , H01L21/469 , H01L21/8242
CPC分类号： H01L21/76801 , C23C16/401 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/31612 , H01L21/7682 , H01L21/76837
摘要： A TEOS deposition method. A mixture of gases is introduced into a process chamber, in which the mixture of gases comprises tetra-ethyl-ortho-silicate (TEOS) and N2. Compressive stress of a TEOS oxide film is increased by activating the mixture of gases.
摘要翻译： TEOS沉积法。将气体混合物引入处理室，其中气体混合物包括四乙基原硅酸盐（TEOS）和N 2。通过激活气体混合物来增加TEOS氧化膜的压缩应力。

88. 发明申请

US20080061343A1 Metal-oxide-metal structure with improved capacitive coupling area 审中-公开
标题翻译：具有改善电容耦合面积的金属氧化物 - 金属结构
公开(公告)号：US20080061343A1
公开(公告)日：2008-03-13
申请号：US11518470
申请日：2006-09-08
申请人： Chin Kun Lan , Sheng-Wen Chen , Hung Jui Chang , Yu-Ku Lin , Ying-Lang Wang
发明人： Chin Kun Lan , Sheng-Wen Chen , Hung Jui Chang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L29/94
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A stacked metal-oxide-metal (MOM) capacitor structure and method of forming the same to increase an electrode/capacitor dielectric coupling area to increase a capacitance, the MOM capacitor structure including a plurality of metallization layers in stacked relationship; wherein each metallization layer includes substantially parallel spaced apart conductive electrode line portions having a first intervening capacitor dielectric; and, wherein the conductive electrode line portions are electrically interconnected between metallization layers by conductive damascene line portions formed in a second capacitor dielectric and disposed underlying the conductive electrode line portions.
摘要翻译：一种堆叠的金属氧化物金属（MOM）电容器结构及其形成方法，以增加电极/电容器介质耦合面积以增加电容，所述MOM电容器结构包括堆叠关系的多个金属化层; 其中每个金属化层包括具有第一中间电容器电介质的基本上平行的隔开的导电电极线部分; 并且其中所述导电电极线部分通过形成在第二电容器电介质中并设置在所述导电电极线部分下方的导电镶嵌线部分在金属化层之间电互连。

89. 发明授权

US07078336B2 Method and system for fabricating a copper barrier layer with low dielectric constant and leakage current 有权
标题翻译：具有低介电常数和漏电流的铜阻挡层的制造方法和系统
公开(公告)号：US07078336B2
公开(公告)日：2006-07-18
申请号：US10716818
申请日：2003-11-19
申请人： Yi-Lung Cheng , Ying-Lang Wang
发明人： Yi-Lung Cheng , Ying-Lang Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76807 , H01L21/76831
摘要： A method is disclosed for reducing metal diffusion in a semiconductor device. After forming a first metal portion over a substrate, a silicon carbon nitro-oxide (SiCNO) layer is deposited on the first metal portion. A dielectric layer is deposited over the SiCNO layer, and an opening is generated in the SiCNO layer and the dielectric layer for a second metal portion to be connected to the first metal portion, wherein the SiCNO layer reduces the diffusion of the first metal portion into the dielectric layer.
摘要翻译：公开了一种用于减少半导体器件中的金属扩散的方法。在衬底上形成第一金属部分之后，在第一金属部分上沉积硅碳氧化物（SiCNO）层。在SiCNO层上沉积介电层，在SiCNO层和第二金属部分的介电层上产生开口以连接到第一金属部分，其中SiCNO层将第一金属部分的扩散减少到电介质层。

90. 发明申请

US20060051973A1 Method for forming IMD films 有权
标题翻译：形成IMD膜的方法
公开(公告)号：US20060051973A1
公开(公告)日：2006-03-09
申请号：US10937215
申请日：2004-09-09
申请人： Yi-Lung Cheng , Miao-Cheng Liao , Ying-Lang Wang
发明人： Yi-Lung Cheng , Miao-Cheng Liao , Ying-Lang Wang
IPC分类号： H01L21/469
CPC分类号： H01L21/76807
摘要： A method for forming IMD films. A substrate is provided. A plurality of dielectric films are formed on the substrate, wherein each of the dielectric layers are deposited in-situ in one chamber with only one thermal cycle.
摘要翻译：一种形成IMD膜的方法。提供基板。在基板上形成多个电介质膜，其中每个电介质层原位沉积在仅具有一个热循环的一个室中。

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