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    • 82. 发明授权
    • PCM signal generating/reproducing apparatus
    • PCM信号生成/再现装置
    • US4961204A
    • 1990-10-02
    • US353709
    • 1989-05-18
    • Hiromichi TanakaTakao AraiToshifumi TakeuchiSeiichi Saito
    • Hiromichi TanakaTakao AraiToshifumi TakeuchiSeiichi Saito
    • G11B20/10G11B20/18H03M13/27H04N5/928
    • H04N5/928G11B20/1809
    • A PCM signal processing apparatus for recording or reproducing a PCM signal. The PCM signal reproducing apparatus of the invention is constituted by: a data addition circuit for receiving a first signal composed of n bits per word (n being an integer) and a second signal composed of n' bits per word (n' being an integer) as mode inputs different from each other, and for adding fixed data of (n-n') bits to every word of the second signal to thereby generate a third signal; a first switch device for receiving the first and third signals and for selectively outputting one of the first and third signals; a symbol generation circuit for converting every word of the output of the first switch device into symbol data of m.times.l bits (n>l); a signal processing circuit for performing at least interleave processing, error correction code generating processing, and addition of a synchronizing signal, on the output of the symbol generation circuit, to thereby generate a first data frame; a data deletion circuit for deleting the fixed data from the first data frame of the signal processing circuit to thereby generate a second data frame; and a second switch devices for receiving the first data frame from the signal processing circuit and the second data frame from the data deletion circuit.
    • 一种用于记录或再现PCM信号的PCM信号处理装置。 本发明的PCM信号再现装置由以下部分构成:数据加法电路,用于接收由每个字n位(n为整数)组成的第一信号和由每个字n位(n'为整数)组成的第二信号 )作为彼此不同的模式输入,并且用于将(n-n')位的固定数据添加到第二信号的每个字,从而生成第三信号; 第一开关装置,用于接收第一和第三信号并选择性地输出第一和第三信号之一; 符号产生电路,用于将第一开关装置的输出的每个字转换成m×1位(n> 1)的符号数据; 信号处理电路,用于在符号生成电路的输出上执行至少交织处理,纠错码生成处理以及同步信号的相加,从而生成第一数据帧; 数据删除电路,用于从信号处理电路的第一数据帧中删除固定数据,从而生成第二数据帧; 以及用于从信号处理电路接收第一数据帧的第二开关装置和来自数据删除电路的第二数据帧。
    • 87. 发明授权
    • Semiconductor integrated circuit and operation method for the same
    • 半导体集成电路及其运算方法相同
    • US07948298B2
    • 2011-05-24
    • US12851175
    • 2010-08-05
    • Tadashi KameyamaTakayasu ItoSeiichi SaitoKoji Sato
    • Tadashi KameyamaTakayasu ItoSeiichi SaitoKoji Sato
    • H01L35/00
    • G05F3/30G05F3/227
    • The semiconductor integrated circuit is provided, in which an external temperature control or temperature monitoring is possible, with little influence by the noise of a system board which mounts the semiconductor integrated circuit. The semiconductor integrated circuit includes the temperature detection circuit which detects the chip temperature, and the functional module which flows a large operating current. An external terminal which supplies operating voltage, and an external terminal which supplies ground voltage are coupled to the functional module. The temperature detection circuit generates a temperature detection signal and a reference signal. The reference signal and the temperature detection signal are led out to the exterior of the semiconductor integrated circuit via a first external output terminal and a second external output terminal, respectively, and are supplied to an external temperature control/monitoring circuit which has a circuitry type of a differential amplifier circuit.
    • 提供了半导体集成电路,其中可以进行外部温度控制或温度监视,几乎不受安装半导体集成电路的系统板的噪声的影响。 半导体集成电路包括检测芯片温度的温度检测电路和流过大的工作电流的功能模块。 提供工作电压的外部端子和提供接地电压的外部端子耦合到功能模块。 温度检测电路产生温度检测信号和参考信号。 参考信号和温度检测信号分别经由第一外部输出端子和第二外部输出端子被引出到半导体集成电路的外部,并且被提供给具有电路类型的外部温度控制/监视电路 的差分放大电路。
    • 90. 发明申请
    • SEMICONDUCTOR DATA PROCESSING DEVICE AND DATA PROCESSING SYSTEM
    • 半导体数据处理设备和数据处理系统
    • US20100274412A1
    • 2010-10-28
    • US12763283
    • 2010-04-20
    • Seiichi SaitoKatsuo KanemaruTakahiro Oga
    • Seiichi SaitoKatsuo KanemaruTakahiro Oga
    • G06F17/00G06F15/177G06F9/46G06F13/28G06K9/46G06F7/00
    • G06F15/17325
    • The present invention provides an arrangement for enabling a plurality of central processing units to share specific resources while ensuring overall reliability owing to domain separation. More specifically, in a semiconductor data processing device comprising a plurality of access management circuits for managing access to resource units that are sharable by the central processing units via an internal bus, each of the access management circuits performs permission/inhibition control for access from the central processing units to the resource units according to a setting state of a domain setup register so as to allow domain separation of the resource units for each of the central processing units, and through use of a priority access permission control function for specific resource units selectively recognized by the access management circuits as resources sharable by the central processing units, access from one of the central processing units that is identified by register setting data is given higher priority than access from the other central processing units.
    • 本发明提供了一种用于使多个中央处理单元能够共享特定资源同时由于域分离而确保整体可靠性的布置。 更具体地说,在包括多个访问管理电路的半导体数据处理装置中,每个访问管理电路经由内部总线管理对由中央处理单元共享的资源单元的访问,执行用于访问的许可/禁止控制 中央处理单元根据域设置寄存器的设置状态到资源单元,以便允许用于每个中央处理单元的资源单元的域分离,并且通过对特定资源单元选择性地使用优先级访问许可控制功能 由访问管理电路识别为由中央处理单元共享的资源,来自通过寄存器设置数据识别的一个中央处理单元的访问被给予比来自其他中央处理单元的访问更高的优先级。