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81. 发明授权

US07718489B2 Double-gate FETs (field effect transistors) 失效
标题翻译：双栅极FET（场效应晶体管）
公开(公告)号：US07718489B2
公开(公告)日：2010-05-18
申请号：US11436480
申请日：2006-05-18
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： A semiconductor structure and method for forming the same. The structure includes multiple fin regions disposed between first and second source/drain (S/D) regions. The structure further includes multiple front gates and back gates, each of which is sandwiched between two adjacent fin regions such that the front gates and back gates are alternating (i.e., one front gate then one back gate and then one front gate, and so on). The widths of the front gates are greater than the widths of the back gates. The capacitances of between the front gates and the S/D regions are smaller than the capacitances of between the back gates and the S/D regions. The distances between the front gates and the S/D regions are greater than the distances between the back gates and the S/D regions.
摘要翻译：一种半导体结构及其形成方法。该结构包括设置在第一和第二源极/漏极（S / D）区域之间的多个鳍片区域。该结构还包括多个前门和后门，每个前门和后门夹在两个相邻鳍片区域之间，使得前门和后门交替（即，一个前门，然后一个后门，然后一个前门，等等）。前门的宽度大于后门的宽度。前门和S / D区之间的电容小于后门和S / D区之间的电容。前门和S / D区之间的距离大于后门和S / D区之间的距离。

82. 发明申请

US20090295432A1 CMOS BACK-GATED KEEPER TECHNIQUE 失效
公开(公告)号：US20090295432A1
公开(公告)日：2009-12-03
申请号：US12538652
申请日：2009-08-10
申请人： Kerry Bernstein , Andres Bryant , Wilfried Haensch
发明人： Kerry Bernstein , Andres Bryant , Wilfried Haensch
IPC分类号： H03K19/20
CPC分类号： H03K19/0008 , H03K3/356104 , H03K2217/0018
摘要： A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a gate moves inversely to its body potential, it follows then that in general, the body of a given device must be tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate and logical family operation.
摘要翻译：详细描述了利用并接触MOSFET器件的第四端子（衬底/本体）的逻辑电路和栅极的构造和操作的新颖方法。新颖的结构和操作提供了当主动接通（以增加过驱动和性能）时以及在关闭时较高的相对阈值电压（以减少泄漏功率）时将这种体接触的MOSFET器件保持在较低的阈值电压（VTh）。因为门的门限电位与其电位相反地移动，所以一般来说，给定器件的器件必须与器件的漏极电压相反，以达到改善器件所需的阈值电位调制效应，电路，门和逻辑家庭操作。

83. 发明申请

US20090269897A1 METHODS OF FABRICATING DUAL-DEPTH TRENCH ISOLATION REGIONS FOR A MEMORY CELL 审中-公开
标题翻译：制备记忆细胞的双深度分离分离区的方法
公开(公告)号：US20090269897A1
公开(公告)日：2009-10-29
申请号：US12111266
申请日：2008-04-29
申请人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Michael A. Guillorn , Ryoji Hasumi , Edward J. Nowak , Mickey H. Yu
发明人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Michael A. Guillorn , Ryoji Hasumi , Edward J. Nowak , Mickey H. Yu
IPC分类号： H01L21/8234
CPC分类号： H01L21/823481 , H01L27/1104
摘要： Methods for fabricating dual-depth trench isolation regions for a memory cell. First and second deep trench isolation regions are formed in the semiconductor layer that laterally bound a device region in a well of a first conductivity type in the semiconductor layer. First and second pluralities of doped regions of a second conductivity type are formed in the device region. A shallow trench isolation region is formed that extends laterally across the device region from the first deep trench isolation region to the second deep trench isolation region. The shallow trench isolation region is disposed in the device region between the first and second pluralities of doped regions. The shallow trench isolation region extends into the semiconductor layer to a depth such that the well is continuous beneath the shallow trench isolation region. A gate stack controls carrier flow between a pair of the first plurality of doped regions.
摘要翻译：用于制造用于存储单元的双深度沟槽隔离区域的方法。在半导体层中形成第一和第二深沟槽隔离区域，该半导体层横向地限定半导体层中的第一导电类型的阱中的器件区域。在器件区域中形成第二导电类型的第一和第二多个掺杂区域。形成了浅沟槽隔离区域，其横跨穿过器件区域从第一深沟槽隔离区域延伸到第二深沟槽隔离区域。浅沟槽隔离区设置在第一和第二多个掺杂区域之间的器件区域中。浅沟槽隔离区域延伸到半导体层中的深度，使得阱在浅沟槽隔离区域之下是连续的。栅极堆叠控制一对第一多个掺杂区域之间的载流子流动。

84. 发明申请

US20090263949A1 TRANSISTORS HAVING ASYMMETRIC STRAINED SOURCE/DRAIN PORTIONS 有权
标题翻译：具有不对称应变源/漏区的晶体管
公开(公告)号：US20090263949A1
公开(公告)日：2009-10-22
申请号：US12104475
申请日：2008-04-17
申请人： Brent Alan Anderson , Andres Bryant , Edward Joseph Nowak
发明人： Brent Alan Anderson , Andres Bryant , Edward Joseph Nowak
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/66795 , H01L29/785
摘要： A structure formation method. First, a structure is provided including (a) a fin region comprising (i) a first source/drain portion having a first surface and a third surface parallel to each other, not coplanar, and both exposed to a surrounding ambient, (ii) a second source/drain portion having a second surface and a fourth surface parallel to each other, not coplanar, and both exposed to the surrounding ambient, and (iii) a channel region disposed between the first and second source/drain portions, (b) a gate dielectric layer, and (c) a gate electrode region, wherein the gate dielectric layer (i) is sandwiched between, and (ii) electrically insulates the gate electrode region and the channel region. Next, a patterned covering layer is used to cover the first and second surfaces but not the third and fourth surfaces. Then, the first and second source/drain portions are etched at the third and fourth surfaces, respectively.
摘要翻译：一种结构形成方法。首先，提供一种结构，其包括（a）翅片区域，其包括：（i）第一源极/漏极部分，其具有彼此平行的第一表面和第三表面，不共面，并且暴露于周围环境;（ii）第二源极/漏极部分，具有彼此平行的第二表面和第四表面，不共面，并暴露于周围环境;以及（iii）设置在第一和第二源极/漏极部分之间的沟道区域，（b ）栅介质层，和（c）栅电极区，其中所述栅介质层（i）夹在其间，和（ii）使所述栅电极区和所述沟道区电绝缘。接下来，使用图案化覆盖层来覆盖第一表面和第二表面而不是第三表面和第四表面。然后，分别在第三和第四表面处蚀刻第一和第二源极/漏极部分。

85. 发明申请

US20090261415A1 FULLY-DEPLETED LOW-BODY DOPING FIELD EFFECT TRANSISTOR (FET) WITH REVERSE SHORT CHANNEL EFFECTS (SCE) INDUCED BY SELF-ALIGNED EDGE BACK-GATE(S) 有权
标题翻译：具有反向短路通道效应（SCE）的全自动低体积场效应晶体管（FET）由自对准边缘背栅（S）
公开(公告)号：US20090261415A1
公开(公告)日：2009-10-22
申请号：US12104683
申请日：2008-04-17
申请人： James W. Adkisson , Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
发明人： James W. Adkisson , Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
IPC分类号： H01L49/00 , H01L21/00
CPC分类号： H01L29/78603 , H01L29/66621 , H01L29/78645 , H01L29/78648 , H01L29/78696
摘要： Disclosed are embodiments of a field effect transistor (FET) and, more particularly, a fully-depleted, thin-body (FDTB) FET that allows for scaling with minimal short channel effects, such as drain induced barrier lowering (DIBL) and saturation threshold voltage (Vtsat) roll-off, at shorter channel lengths. The FDTB FET embodiments are configured with either an edge back-gate or split back-gate that can be biased in order to selectively adjust the potential barrier between the source/drain regions and the channel region for minimizing off-state leakage current between the drain region and the source region and/or for varying threshold voltage. These unique back-gate structures avoid the need for halo doping to ensure linear threshold voltage (Vtlin) roll-up at smaller channel lengths and, thus, avoid across-chip threshold voltage variations due to random doping fluctuations. Also disclosed are method embodiments for forming such FETs.
摘要翻译：公开了场效应晶体管（FET）的具体实施例，更具体地说，是允许以最小的短沟道效应（例如漏极感应势垒降低（DIBL）和饱和阈值））进行缩放的完全耗尽的薄体（FDTB）FET 电压（Vtsat）滚降，通道长度较短。 FDTB FET实施例配置有可被偏置的边缘背栅极或分支反向栅极，以便选择性地调节源极/漏极区域和沟道区域之间的势垒，以最小化漏极之间的截止状态漏电流区域和源极区域和/或用于改变阈值电压。这些独特的背栅结构避免了对光晕掺杂的需要，以确保较小通道长度的线性阈值电压（Vtlin）汇总，从而避免由于随机掺杂波动引起的跨芯片阈值电压变化。还公开了用于形成这种FET的方法实施例。

86. 发明申请

US20090243000A1 METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS 有权
标题翻译：定制SOI电路历史效应的方法，结构与设计结构
公开(公告)号：US20090243000A1
公开(公告)日：2009-10-01
申请号：US12055686
申请日：2008-03-26
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/78 , H01L21/283 , G06F17/50
CPC分类号： H01L29/78 , H01L29/42384 , H01L29/4908 , H01L29/512 , H01L29/7841
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed over an active region of a FET and a low-leakage dielectric formed on the active region and adjacent the high-leakage dielectric. The low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括在FET的有源区上形成的高泄漏电介质和形成在有源区上并与高泄漏电介质相邻的低泄漏电介质。低泄漏电介质具有比高泄漏电介质低的漏电流。还提供了一种制造该结构的结构和方法。

87. 发明申请

US20090189223A1 Complementary Metal Gate Dense Interconnect and Method of Manufacturing 有权
标题翻译：互补金属门密集互连和制造方法
公开(公告)号：US20090189223A1
公开(公告)日：2009-07-30
申请号：US12022292
申请日：2008-01-30
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823842 , H01L21/76895 , H01L21/823871
摘要： Complementary metal gate dense interconnects and methods of manufacturing the interconnects is provided. The method comprises forming a first metal gate on a wafer and second metal gate on the wafer. A conductive interconnect material is deposited in a space formed between the first metal gate and the second metal gate to provide an electrical connection between the first metal gate and the second metal gate.
摘要翻译：提供互补金属栅极致密互连和制造互连的方法。该方法包括在晶片上形成第一金属栅极和在晶片上形成第二金属栅极。导电互连材料沉积在形成在第一金属栅极和第二金属栅极之间的空间中，以在第一金属栅极和第二金属栅极之间提供电连接。

88. 发明申请

US20090179232A1 LOW LAG TRANSFER GATE DEVICE 有权
标题翻译： LOW LAG传输闸门装置
公开(公告)号：US20090179232A1
公开(公告)日：2009-07-16
申请号：US12013817
申请日：2008-01-14
申请人： James W. Adkisson , Andres Bryant , John J. Ellis-Monaghan
发明人： James W. Adkisson , Andres Bryant , John J. Ellis-Monaghan
IPC分类号： H01L27/146
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14612
摘要： A CMOS active pixel sensor (APS) cell structure includes at least one transfer gate device and method of operation. A first transfer gate device comprises a diodic or split transfer gate conductor structure having a first doped region of first conductivity type material and a second doped region of a second conductivity type material. A photosensing device is formed adjacent the first doped region for collecting charge carriers in response to light incident thereto, and, a diffusion region of a second conductivity type material is formed at or below the substrate surface adjacent the second doped region of the transfer gate device for receiving charges transferred from the photosensing device while preventing spillback of charges to the photosensing device upon timed voltage bias to the diodic or split transfer gate conductor structure. Alternately, an intermediate charge storage device and second transfer gate device may be provided which may first temporarily receive charge carriers from the photosensing device, and, upon activating the second transfer gate device in a further timed fashion, read out the charge stored at the intermediate charge storage device for transfer to the second transfer gate device while preventing spillback of charges to the photosensing device. The APS cell structure is further adapted for a global shutter mode of operation, and further comprises a light shield element is further provided to ensure no light reaches the photosensing and charge storage devices during charge transfer operation.
摘要翻译： CMOS有源像素传感器（APS）单元结构包括至少一个传输栅极器件和操作方法。第一传输栅极器件包括具有第一导电类型材料的第一掺杂区域和第二导电类型材料的第二掺杂区域的二极或分裂传输栅极导体结构。光敏装置形成在第一掺杂区域附近，用于响应于入射到其上的光而收集电荷载流子，并且第二导电类型材料的扩散区域形成在与传输栅极器件的第二掺杂区域相邻的衬底表面处或下方用于接收从光敏装置转移的电荷，同时防止在针对二极或分离转移栅极导体结构的定时电压偏压时对光敏装置的电荷溢出。或者，可以提供中间电荷存储装置和第二传输门装置，其可以首先临时从光敏装置接收电荷载体，并且在以另外的定时方式激活第二传输门装置时，读出存储在中间电荷存储装置，用于传送到第二传输门装置，同时防止电荷向光感器件溢出。 APS单元结构进一步适用于全局快门操作模式，并且进一步包括遮光元件，以在电荷转移操作期间确保没有光到达光敏和电荷存储装置。

89. 发明申请

US20090057781A1 MUGFET WITH OPTIMIZED FILL STRUCTURES 有权
标题翻译：具有优化填充结构的MUGFET
公开(公告)号：US20090057781A1
公开(公告)日：2009-03-05
申请号：US11846825
申请日：2007-08-29
申请人： Brent Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/94 , H01L29/76
CPC分类号： H01L27/0629 , H01L21/823431 , H01L27/0886 , H01L29/66795 , H01L29/785
摘要： A semiconductor structure includes active multi-gate fin-type field effect transistor (MUGFET) structures and inactive MUGFET fill structures between the active MUGFET structures. The active MUGFET structures comprise transistors that change conductivity depending upon voltages within gates of the active MUGFET structures. Conversely, the inactive MUGFET fill structures comprise passive devices that do not change conductivity irrespective of voltages within gates of the inactive MUGFET fill structures. The gates of the active MUGFET structures are parallel to the gates of the inactive MUGFET fill structures, and the fins of the active MUGFET structures are the same size as the fins of the inactive MUGFET fill structures. The active MUGFET structures have the same pitch as the gates of the inactive MUGFET fill structures. The gates of the active MUGFET structures comprise active doping agents, but the inactive MUGFET fill structures do not contain the active doping agents.
摘要翻译：半导体结构包括有源多栅极鳍型场效应晶体管（MUGFET）结构和在活性MUGFET结构之间的无活性MUGFET填充结构。活性MUGFET结构包括根据活性MUGFET结构的门内的电压改变导电性的晶体管。相反，无活性的MUGFET填充结构包括不影响无活性MUGFET填充结构的门内的电压的电导率的无源器件。活动MUGFET结构的门平行于非活性MUGFET填充结构的门，并且活动MUGFET结构的翅片与非活性MUGFET填充结构的翅片的尺寸相同。活动的MUGFET结构具有与非活性MUGFET填充结构的门相同的间距。活性MUGFET结构的栅极包含活性掺杂剂，但是不活泼的MUGFET填充结构不含活性掺杂剂。

90. 发明申请

US20080268588A1 RECESSED GATE CHANNEL WITH LOW Vt CORNER 有权
标题翻译：具有低Vt角的后门通道
公开(公告)号：US20080268588A1
公开(公告)日：2008-10-30
申请号：US11741898
申请日：2007-04-30
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L21/8238 , H01L27/01
CPC分类号： H01L29/665 , H01L29/1083 , H01L29/4236 , H01L29/517 , H01L29/66621 , H01L29/78
摘要： A recessed gate FET device includes a substrate having an upper and lower portions, the lower portion having a reduced concentration of dopant material than the upper portion; a trench-type gate electrode defining a surrounding channel region and having a gate dielectric material layer lining and including a conductive material having a top surface recessed to reduce overlap capacitance with respect to the source and drain diffusion regions formed at an upper substrate surface at either side of the gate electrode. There is optionally formed halo implants at either side of and abutting the gate electrode, each halo implants extending below the source and drain diffusions into the channel region. Additionally, highly doped source and drain extension regions are formed that provide a low resistance path from the source and drain diffusion regions to the channel region. The recessed gate FET device suppresses short channel effects and exhibits improved threshold voltage (Vt) characteristics at corners of the trench bottom.
摘要翻译：凹陷栅极FET器件包括具有上部和下部的衬底，下部具有比上部更低的掺杂剂材料的浓度; 限定周围通道区域并且具有衬底的栅介质材料层的沟槽型栅电极，并且包括具有凹陷的顶表面的导电材料，以减少相对于在上基板表面处形成的源极和漏极扩散区域的重叠电容侧电极。在栅电极的任一侧和邻接栅电极处可选地形成卤素植入物，每个卤素注入物延伸到源极和漏极扩散到沟道区域之内。此外，形成高掺杂的源极和漏极延伸区域，其提供从源极和漏极扩散区域到沟道区域的低电阻路径。凹陷栅极FET器件抑制短沟道效应并且在沟槽底部的拐角处表现出改进的阈值电压（Vt）特性。

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