专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US07800932B2 Memory cell comprising switchable semiconductor memory element with trimmable resistance 有权
标题翻译：存储单元包括具有可调整电阻的可切换半导体存储元件
公开(公告)号：US07800932B2
公开(公告)日：2010-09-21
申请号：US11237167
申请日：2005-09-28
申请人： Tanmay Kumar , S. Brad Herner
发明人： Tanmay Kumar , S. Brad Herner
IPC分类号： G11C11/00 , G11C11/14 , G11C11/15
CPC分类号： G11C11/5692 , G11C11/005 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C17/14 , G11C2211/5641 , G11C2211/5646 , G11C2213/32 , G11C2213/71 , G11C2213/72 , G11C2213/76 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/148
摘要： A nonvolatile memory cell comprising doped semiconductor material and a diode can store memory states by changing the resistance of the doped semiconductor material by application of a set pulse (decreasing resistance) or a reset pulse (increasing resistance.) Set pulses are of short duration and above a threshold voltage, while reset pulses are longer duration and below a threshold voltage. In some embodiments multiple resistance states can be achieved, allowing for a multi-state cell, while restoring a prior high-resistance state allows for an rewriteable cell. In some embodiments, the diode and a switchable memory formed of doped semiconductor material are formed in series, while in other embodiments, the diode itself serves as the semiconductor switchable memory element.
摘要翻译：包括掺杂半导体材料和二极管的非易失性存储单元可以通过施加设置脉冲（降低电阻）或复位脉冲（增加电阻）来改变掺杂半导体材料的电阻来存储存储器状态。设置脉冲的持续时间短，高于阈值电压，而复位脉冲的持续时间更长并低于阈值电压。在一些实施例中，可以实现多个电阻状态，允许多状态单元，同时恢复先前的高电阻状态允许可重写单元。在一些实施例中，二极管和由掺杂半导体材料形成的可切换存储器是串联形成的，而在其它实施例中，二极管本身用作半导体可切换存储元件。

82. 发明授权

US07754605B2 Ultrashallow semiconductor contact by outdiffusion from a solid source 有权
标题翻译：超固体半导体从固体源扩散接触
公开(公告)号：US07754605B2
公开(公告)日：2010-07-13
申请号：US11478706
申请日：2006-06-30
申请人： S. Brad Herner , Steven J Radigan
发明人： S. Brad Herner , Steven J Radigan
IPC分类号： H01L21/443
CPC分类号： H01L27/1021 , H01L21/02425 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/2254
摘要： The surface of a conductive layer such as a conductive nitride, a conductive silicide, a metal, or metal alloy or compound, is exposed to a dopant gas which provides an n-type or p-type dopant. The dopant gas may be included in a plasma. Semiconductor material, such as silicon, germanium, or their alloys, is deposited directly on the surface which has been exposed to the dopant gas. During and subsequent to deposition, dopant atoms diffuse into the deposited semiconductor, forming a thin heavily doped region and making a good ohmic contact between the semiconductor material and the underlying conductive layer.
摘要翻译：诸如导电氮化物，导电硅化物，金属或金属合金或化合物的导电层的表面暴露于提供n型或p型掺杂剂的掺杂气体。掺杂气体可以包括在等离子体中。诸如硅，锗或其合金的半导体材料直接沉积在暴露于掺杂气体的表面上。在沉积期间和之后，掺杂剂原子扩散到沉积的半导体中，形成薄的重掺杂区域，并在半导体材料和下面的导电层之间形成良好的欧姆接触。

83. 发明申请

US20100163831A1 DEPOSITED SEMICONDUCTOR STRUCTURE TO MINIMIZE N-TYPE DOPANT DIFFUSION AND METHOD OF MAKING 有权
标题翻译：沉积半导体结构以最小化N型掺杂物扩散和制备方法
公开(公告)号：US20100163831A1
公开(公告)日：2010-07-01
申请号：US12632013
申请日：2009-12-07
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L45/00
CPC分类号： H01L45/08 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L29/161 , H01L29/165 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： A microelectronic structure including a layerstack is provided, the layerstack including: (a) a first layer including semiconductor material that is very heavily n-doped before being annealed, having a first-layer before-anneal dopant concentration, the first layer being between about 50 and 200 angstroms thick, wherein the first layer is above a substrate, and wherein the first layer is heavily n-doped after being annealed, having a first-layer after-anneal dopant concentration, the first-layer before-anneal dopant concentration exceeding the first-layer after-anneal concentration; (b) a second layer including semiconductor material that is not heavily doped before being annealed, having a second-layer before-anneal dopant concentration, the second layer being about as thick as the first layer, wherein the second layer is above and in contact with the first layer, and wherein the second layer includes heavily n-doped semiconductor material after being annealed, having a second-layer after-anneal dopant concentration, the second-layer after-anneal dopant concentration exceeding the second-layer before-anneal concentration; and (c) a third layer including semiconductor material that is above and in contact with the second layer and that is not heavily n-doped before or after being annealed, the third layer having a third-layer dopant concentration.
摘要翻译：提供了包括层叠的微电子结构，所述层叠包括：（a）包括半导体材料的第一层，所述第一层包括在退火之前非常重掺杂的半导体材料，具有第一层预退火掺杂剂浓度，所述第一层在约 50和200埃厚，其中第一层位于衬底之上，并且其中第一层在退火之后被重掺杂，具有第一层退火后掺杂剂浓度，第一层预退火掺杂剂浓度超过第一层退火后浓度; （b）包含半导体材料的第二层，其在退火之前未被重掺杂，具有第二层预退火掺杂剂浓度，所述第二层约为第一层厚度，其中第二层高于并接触并且其中所述第二层在退火之后包括重度n掺杂的半导体材料，具有第二层后退火掺杂剂浓度，所述第二层后退火掺杂剂浓度超过所述第二层预退火后浓度 ; 和（c）包含半导体材料的第三层，所述第三层包括在第二层之上并与第二层接触并且在退火之前或之后不重掺杂的半导体材料，第三层具有第三层掺杂剂浓度。

84. 发明授权

US07684226B2 Method of making high forward current diodes for reverse write 3D cell 有权
标题翻译：制造反向写入3D电池的高正向电流二极管的方法
公开(公告)号：US07684226B2
公开(公告)日：2010-03-23
申请号：US11819079
申请日：2007-06-25
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： G11C17/00
CPC分类号： G11C11/36 , H01L27/1021
摘要： A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell including a diode and a metal oxide antifuse dielectric layer over the first electrode, and forming a second electrode over the at least one nonvolatile memory cell. In use, the diode acts as a read/write element of the nonvolatile memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.
摘要翻译：一种制造非易失性存储器件的方法包括：形成第一电极，在所述第一电极上形成至少一个包括二极管和金属氧化物反熔丝电介质层的非易失性存储单元，以及在所述至少一个非易失性存储单元上形成第二电极。在使用中，响应于施加的偏压，二极管通过从第一电阻率状态切换到不同于第一电阻率状态的第二电阻率状态来充当非易失性存储单元的读/写元件。

85. 发明授权

US07682920B2 Method for making a p-i-n diode crystallized adjacent to a silicide in series with a dielectric antifuse 有权
标题翻译：制造与绝缘反熔丝串联的硅化物附近的p-i-n二极管的方法
公开(公告)号：US07682920B2
公开(公告)日：2010-03-23
申请号：US11560283
申请日：2006-11-15
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L21/331
CPC分类号： H01L23/5252 , G11C13/0069 , G11C17/16 , G11C2013/009 , G11C2213/33 , H01L27/1021 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method is described for forming a nonvolatile one-time-programmable memory cell having reduced programming voltage. A contiguous p-i-n diode is paired with a dielectric rupture antifuse formed of a high-dielectric-constant material, having a dielectric constant greater than about 8. In preferred embodiments, the high-dielectric-constant material is formed by atomic layer deposition. The diode is preferably formed of deposited low-defect semiconductor material, crystallized in contact with a silicide. A monolithic three dimensional memory array of such cells can be formed in stacked memory levels above the wafer substrate.
摘要翻译：描述了一种用于形成具有降低的编程电压的非易失性一次可编程存储单元的方法。连续的p-i-n二极管与由介电常数大于约8的高介电常数材料形成的介电破裂反熔丝配对。在优选实施例中，通过原子层沉积形成高介电常数材料。二极管优选由沉积的低缺陷半导体材料形成，与硅化物接触结晶。这种单元的单片三维存储器阵列可以形成在晶片衬底上方的堆叠存储器级中。

86. 发明授权

US07618850B2 Method of making a diode read/write memory cell in a programmed state 有权
标题翻译：使二极管读/写存储单元处于编程状态的方法
公开(公告)号：US07618850B2
公开(公告)日：2009-11-17
申请号：US11693845
申请日：2007-03-30
申请人： Tanmay Kumar , S. Brad Herner
发明人： Tanmay Kumar , S. Brad Herner
IPC分类号： H01L21/82
CPC分类号： G11C13/0069 , G11C11/5692 , G11C17/14 , G11C17/165 , G11C17/18 , G11C2013/0073 , H01L27/101 , H01L27/1021 , H01L29/868
摘要： A method of making a nonvolatile memory device includes fabricating a diode in a low resistivity, programmed state without an electrical programming step. The memory device includes at least one memory cell. The memory cell is constituted by the diode and electrically conductive electrodes contacting the diode.
摘要翻译：制造非易失性存储器件的方法包括在没有电气编程步骤的情况下制造低电阻率编程状态的二极管。存储器件包括至少一个存储单元。存储单元由二极管和与二极管接触的导电电极构成。

87. 发明申请

US20090242031A1 Photovoltaic Assembly Including a Conductive Layer Between a Semiconductor Lamina and a Receiver Element 审中-公开
标题翻译：包括半导体衬底和接收器元件之间的导电层的光伏组件
公开(公告)号：US20090242031A1
公开(公告)日：2009-10-01
申请号：US12057274
申请日：2008-03-27
申请人： S. Brad Herner , Aditya Agarwal
发明人： S. Brad Herner , Aditya Agarwal
IPC分类号： H01L31/028 , H01L31/04 , H01L21/18
CPC分类号： H01L31/068 , H01L31/075 , H01L31/1896 , Y02E10/547 , Y02E10/548
摘要： A semiconductor donor body is affixed to a receiver element, and a thin semiconductor lamina is cleaved from the donor body, remaining affixed to the receiver element. A photovoltaic assembly is fabricated which includes the lamina and the receiver element, wherein a photovoltaic cell comprises the lamina. The bond between the semiconductor donor body and the receiver element must survive processing to complete the cell, as well as eventual assembly, transport, and operation in a finished photovoltaic module. It has been found that inclusion of a conductive layer such as titanium or aluminum aids bonding between the semiconductor donor body and the receiver element. In some embodiments, the conductive layer may also serve as an electrical contact and/or as a reflective layer.
摘要翻译：将半导体施主体固定到接收器元件，并且将薄的半导体层从施主体断开，保持固定在接收器元件上。制造包括层板和接收器元件的光伏组件，其中光伏电池包括层板。半导体施主体和接收元件之间的结合必须能够经受处理以完成电池，以及在成品光伏模块中的最终组装，运输和操作。已经发现，诸如钛或铝的导电层的包含有助于在半导体施主体和接收体之间粘合。在一些实施例中，导电层还可以用作电接触和/或作为反射层。

88. 发明申请

US20090194162A1 METHOD TO FORM A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA 失效
公开(公告)号：US20090194162A1
公开(公告)日：2009-08-06
申请号：US12026530
申请日：2008-02-05
申请人： Srinivasan Sivaram , Aditya Agarwal , S. Brad Herner , Christopher J. Petti
发明人： Srinivasan Sivaram , Aditya Agarwal , S. Brad Herner , Christopher J. Petti
IPC分类号： H01L31/028 , H01L21/00 , H01L31/04
CPC分类号： H01L31/022425 , H01L31/0682 , H01L31/0747 , H01L31/1804 , H01L31/1892 , Y02E10/547 , Y02P70/521
摘要： A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only.

89. 发明申请

US20090181515A1 Selective germanium deposition for pillar devices 有权
标题翻译：支柱装置的选择性锗沉积
公开(公告)号：US20090181515A1
公开(公告)日：2009-07-16
申请号：US12007780
申请日：2008-01-15
申请人： S. Brad Herner , Christopher J. Petti
发明人： S. Brad Herner , Christopher J. Petti
IPC分类号： H01L21/329
CPC分类号： H01L29/868 , H01L27/1021
摘要： A method of making a pillar device includes providing an insulating layer having an opening, and selectively depositing germanium or germanium rich silicon germanium semiconductor material into the opening to form the pillar device.
摘要翻译：制造柱装置的方法包括提供具有开口的绝缘层，并且将锗或富锗硅锗半导体材料选择性地沉积到开口中以形成柱装置。

90. 发明授权

US07560339B2 Nonvolatile memory cell comprising a reduced height vertical diode 有权
标题翻译：非易失性存储单元包括减小的高度的垂直二极管
公开(公告)号：US07560339B2
公开(公告)日：2009-07-14
申请号：US11866403
申请日：2007-10-02
申请人： S. Brad Herner , Steven J. Radigan
发明人： S. Brad Herner , Steven J. Radigan
IPC分类号： H01L29/80
CPC分类号： G11C5/02 , G11C11/39 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L27/1021 , H01L29/0649 , H01L29/66272 , H01L29/732 , H01L29/868
摘要： A nonvolatile memory cell according to the present invention comprises a bottom conductor, a semiconductor pillar, and a top conductor. The semiconductor pillar comprises a junction diode, including a bottom heavily doped region, a middle intrinsic or lightly doped region, and a top heavily doped region, wherein the conductivity types of the top and bottom heavily doped region are opposite. The junction diode is vertically oriented and is of reduced height, between about 500 angstroms and about 3500 angstroms. A monolithic three dimensional memory array of such cells can be formed comprising multiple memory levels, the levels monolithically formed above one another.
摘要翻译：根据本发明的非易失性存储单元包括底部导体，半导体柱和顶部导体。半导体柱包括结二极管，其包括底部重掺杂区域，中间固有或轻掺杂区域和顶部重掺杂区域，其中顶部和底部重掺杂区域的导电类型相反。结二极管是垂直取向的，并且具有降低的高度，在约500埃至约3500埃之间。可以形成这样的单元的单片三维存储器阵列，其包括多个存储器级，电平彼此整体地形成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式