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81. 发明授权

US07923868B2 Method and apparatus for adjusting a power supply of an integrated circuit 有权
标题翻译：用于调整集成电路的电源的方法和装置
公开(公告)号：US07923868B2
公开(公告)日：2011-04-12
申请号：US12012761
申请日：2008-02-05
申请人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
发明人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H02J3/00
CPC分类号： H03K19/0027 , G06F1/3203 , H03K19/00384 , Y10T307/74
摘要： Disclosed is a circuit configured to apply a supply voltage to a switching element (e.g., a transistor). The circuit includes a latch and a processor. The latch is configured to sample a voltage of an output signal of the switching element, and the processor is configured to generate a power adjustment signal to adjust the supply voltage based on the voltage sampled by the latch.
摘要翻译：公开了一种被配置为向开关元件（例如，晶体管）施加电源电压的电路。该电路包括一个锁存器和一个处理器。锁存器被配置为对开关元件的输出信号的电压进行采样，并且处理器被配置为产生功率调整信号，以基于由锁存器采样的电压来调节电源电压。

82. 发明授权

US07787515B2 Method and apparatus for generation of asynchronous clock for spread spectrum transmission 有权
标题翻译：用于产生扩频传输的异步时钟的方法和装置
公开(公告)号：US07787515B2
公开(公告)日：2010-08-31
申请号：US11353431
申请日：2006-02-14
申请人： Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , William B. Wilson , Craig B. Ziemer
发明人： Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , William B. Wilson , Craig B. Ziemer
IPC分类号： H04B1/00
CPC分类号： H04L27/0014 , H04B1/7075 , H04L2027/0036
摘要： A circuit for spread spectrum rate control uses a first interpolator to phase interpolate between a first signal and a second signal and generate a first output signal based on a first control signal. A second interpolator is utilized to phase interpolate between a third signal and a fourth signal and generate a second output signal based on a second control signal. A multiplexer is used to select, based on a select signal, the first output signal or the second output signal as a spread spectrum clock (SSCLK). A leap-frog interpolator control is used to generate, in synchronism with the SSCLK, the first control signal based on a first type of phase adjustment request, the second control signal based on a second type of phase adjustment request, and the select signal to switch the multiplexer between the first output signal and the second output signal after allowing for an interpolator settling time when changing the first control signal or the second control signal.
摘要翻译：用于扩频率控制的电路使用第一内插器在第一信号和第二信号之间进行相位插值，并且基于第一控制信号产生第一输出信号。第二内插器用于在第三信号和第四信号之间进行相位插值，并且基于第二控制信号产生第二输出信号。多路复用器用于基于选择信号选择第一输出信号或第二输出信号作为扩频时钟（SSCLK）。跳跃内插器控制用于与SSCLK同步地产生基于第一类型的相位调整请求的第一控制信号，基于第二类型的相位调整请求的第二控制信号，以及选择信号在改变第一控制信号或第二控制信号之后允许内插器稳定时间之后，在第一输出信号和第二输出信号之间切换多路复用器。

83. 发明申请

US20100195777A1 METHOD AND APPARATUS FOR IMPROVING LINEARITY IN CLOCK AND DATA RECOVERY SYSTEMS 有权
标题翻译：用于改进时钟和数据恢复系统中的线性的方法和装置
公开(公告)号：US20100195777A1
公开(公告)日：2010-08-05
申请号：US12755522
申请日：2010-04-07
申请人： Christopher Abel , Joseph Anidjar , Vladimir Sindalovsky , Craig Ziemer
发明人： Christopher Abel , Joseph Anidjar , Vladimir Sindalovsky , Craig Ziemer
IPC分类号： H04L7/033
CPC分类号： H04L7/0008
摘要： Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.
摘要翻译：公开了一种用于提高时钟和数据恢复（CDR）电路的线性度的系统和方法。在一个实施例中，接收数据流，并且使用两个内插器调整时钟信号的相位。第二内插器的输出信号的相位与调整第一内插器的相位同时调整并补充。第一内插器的输出信号被注入到具有多个延迟单元的延迟环中的第一延迟单元中，并且第二内插器的输出被去激活。当达到第一内插器的输出信号的最大相位时，第二内插器的输出信号被注入另一个延迟单元，并且第一内插器的输出信号被去激活。然后使用延迟环路的输出作为时钟信号来恢复数据流。

84. 发明授权

US07724857B2 Method and apparatus for improving linearity in clock and data recovery systems 有权
标题翻译：提高时钟和数据恢复系统线性度的方法和装置
公开(公告)号：US07724857B2
公开(公告)日：2010-05-25
申请号：US11375828
申请日：2006-03-15
申请人： Christopher Abel , Joseph Anidjar , Vladimir Sindalovsky , Craig Ziemer
发明人： Christopher Abel , Joseph Anidjar , Vladimir Sindalovsky , Craig Ziemer
IPC分类号： H04L7/00
CPC分类号： H04L7/0008
摘要： Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.
摘要翻译：公开了一种用于提高时钟和数据恢复（CDR）电路的线性度的系统和方法。在一个实施例中，接收数据流，并且使用两个内插器调整时钟信号的相位。第二内插器的输出信号的相位与调整第一内插器的相位同时调整并补充。第一内插器的输出信号被注入到具有多个延迟单元的延迟环中的第一延迟单元中，并且第二内插器的输出被非激活。当达到第一内插器的输出信号的最大相位时，第二内插器的输出信号被注入另一个延迟单元，并且第一内插器的输出信号被去激活。然后使用延迟环路的输出作为时钟信号来恢复数据流。

85. 发明授权

US07549074B2 Content deskewing for multichannel synchronization 有权
标题翻译：多通道同步的内容去歪斜
公开(公告)号：US07549074B2
公开(公告)日：2009-06-16
申请号：US11143370
申请日：2005-06-02
申请人： Ravikumar K. Charath , Vladimir Sindalovsky , Lane A. Smith
发明人： Ravikumar K. Charath , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： G06F1/12
CPC分类号： H03M9/00 , H04J3/0632 , H04J3/0685
摘要： The various embodiments of the invention provide an apparatus, system and method for data content deskewing among a plurality of data channels for data synchronization. The various embodiments determine whether a data alignment signal has been written, for each data channel of the plurality of data channels, such as a comma character. When a data alignment signal has been written in a data channel of the plurality of data channels, the embodiments determine a corresponding channel location of the data alignment signal for each data channel having the data alignment signal. When each data channel of the plurality of data channels has the data alignment signal, and when the data alignment signal is to be read on a next read cycle in at least one data channel, the various embodiments move a corresponding read pointer for each data channel of the plurality of data channels to the corresponding channel location of the data alignment signal. The data alignment signal is then read in all channels during the next read cycle, followed by subsequent reading of deskewed or otherwise synchronized data, such as for conversion of parallel data into serial data for subsequent data transmission.
摘要翻译：本发明的各种实施例提供了一种用于数据同步的多个数据信道之间的数据内容偏移校正的装置，系统和方法。各种实施例针对多个数据信道中的每个数据信道（诸如逗号字符）确定是否已经写入数据对准信号。当数据对准信号已被写入多个数据通道的数据通道时，这些实施例为具有数据对准信号的每个数据通道确定数据对准信号的相应通道位置。当多个数据信道的每个数据信道具有数据对准信号时，并且当在至少一个数据信道中在下一个读取周期读取数据对准信号时，各种实施例移动每个数据信道的相应读指针多个数据信道的数据对准信号的相应信道位置。然后在下一个读取周期期间在所有通道中读取数据对齐信号，随后读取去偏移或以其他方式同步的数据，例如用于将并行数据转换为串行数据以用于后续数据传输。

86. 发明授权

US07495494B2 Parallel trimming method and apparatus for a voltage controlled delay loop 有权
标题翻译：用于电压控制延迟回路的平行修整方法和装置
公开(公告)号：US07495494B2
公开(公告)日：2009-02-24
申请号：US11141703
申请日：2005-05-31
申请人： Ronald L. Freyman , Mohammad S. Mobin , Vladimir Sindalovsky , Lane A. Smith
发明人： Ronald L. Freyman , Mohammad S. Mobin , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H03H11/26
CPC分类号： H03L7/0814 , H04L7/0337
摘要： A parallel trimming method and apparatus are provided for a voltage controlled delay loop. A plurality of delay units in a voltage controlled delay loop are trimmed. Each delay unit comprises a delay element and a latch buffer. A reference signal is applied to each of the delay units and a position of an edge (such as a rising or falling edge) associated with each of the delay units is identified. The edges of the delay units are then aligned by adjusting a trim setting of the respective latch buffer.
摘要翻译：提供了一种用于电压控制延迟环路的并行修整方法和装置。电压控制延迟环中的多个延迟单元被修整。每个延迟单元包括延迟元件和锁存缓冲器。参考信号被施加到每个延迟单元，并且识别与每个延迟单元相关联的边缘（例如上升沿或下降沿）的位置。然后通过调整相应的锁存缓冲器的修整设置来对准延迟单元的边缘。

87. 发明授权

US07421050B2 Parallel sampled multi-stage decimated digital loop filter for clock/data recovery 有权
标题翻译：用于时钟/数据恢复的并行采样多级抽取数字环路滤波器
公开(公告)号：US07421050B2
公开(公告)日：2008-09-02
申请号：US10965138
申请日：2004-10-14
申请人： Pervez Mirza Aziz , Donald Raymond Laturell , Vladimir Sindalovsky
发明人： Pervez Mirza Aziz , Donald Raymond Laturell , Vladimir Sindalovsky
IPC分类号： H04L7/00
CPC分类号： H03L7/085 , H03D13/006 , H03L7/087 , H03L7/091 , H03L7/093 , H04L7/0054
摘要： The present invention utilizes a parallel sampled multi stage decimated digital loop filter for clock and data recovery function. In particular, the present invention provides multiple sampling clocks, with these clocks having sampling clock phases separated in time. These clocks are used in conjunction with multiple data detectors and phase detectors to efficiently process received analog signals in a decimated loop filter system.
摘要翻译：本发明利用并行采样多级抽取数字环路滤波器进行时钟和数据恢复功能。特别地，本发明提供多个采样时钟，这些时钟具有时间上分离的采样时钟相位。这些时钟与多个数据检测器和相位检测器结合使用，以有效地处理抽取的环路滤波器系统中的接收的模拟信号。

88. 发明申请

US20080191789A1 Method and apparatus for adjusting a power supply of an integrated circuit 有权
标题翻译：用于调整集成电路的电源的方法和装置
公开(公告)号：US20080191789A1
公开(公告)日：2008-08-14
申请号：US12012761
申请日：2008-02-05
申请人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
发明人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： G05F1/10
CPC分类号： H03K19/0027 , G06F1/3203 , H03K19/00384 , Y10T307/74
摘要： Disclosed is a circuit configured to apply a supply voltage to a switching element (e.g., a transistor). The circuit includes a latch and a processor. The latch is configured to sample a voltage of an output signal of the switching element, and the processor is configured to generate a power adjustment signal to adjust the supply voltage based on the voltage sampled by the latch.
摘要翻译：公开了一种被配置为向开关元件（例如，晶体管）施加电源电压的电路。该电路包括一个锁存器和一个处理器。锁存器被配置为对开关元件的输出信号的电压进行采样，并且处理器被配置为产生功率调整信号，以基于由锁存器采样的电压来调节电源电压。

89. 发明申请

US20080001644A1 Phase interpolator with output amplitude correction 有权
公开(公告)号：US20080001644A1
公开(公告)日：2008-01-03
申请号：US11479749
申请日：2006-06-30
申请人： Christopher J. Abel , Joseph Anidjar , Vladimir Sindalovsky , Craig B. Ziemer
发明人： Christopher J. Abel , Joseph Anidjar , Vladimir Sindalovsky , Craig B. Ziemer
IPC分类号： H03K5/13
CPC分类号： H03K5/13 , H03K2005/00052 , H03K2005/00156 , H03K2005/00195
摘要： A phase interpolator generates a phase-interpolated output clock signal Z from two phase-offset input clock signals A and B, where the interpolation angle of the output clock is based on a weight value W. The phase interpolator has A-side and B-side circuitry, each having (1) an array of parallel current mirrors, (2) a block of parallel switches, where each switch is connected in series with a corresponding current mirror, and (3) an encoder that controls the corresponding switches based on the weight value W. The total current through the phase interpolator varies with interpolation angle, such that, for example, the variation in output amplitude with interpolation angle is reduced. In general, individual bit values in weight value W are not used to control individual switches for all interpolation angles.

90. 发明授权

US07312667B2 Statically controlled clock source generator for VCDL clock phase trimming 失效
标题翻译：用于VCDL时钟相位修整的静态时钟源发生器
公开(公告)号：US07312667B2
公开(公告)日：2007-12-25
申请号：US11221316
申请日：2005-09-07
申请人： Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith , Craig B. Ziemer
发明人： Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith , Craig B. Ziemer
IPC分类号： H03B27/00
CPC分类号： H03L7/00 , H04L7/0337
摘要： The present invention addresses the generation of a controlled clock source for use in trimming VCDL delay line output clocks. In this trimming process, adjustments are made for static variations in these output clocks. The invention's use of a controlled clock source eliminates the need for this trimming process to be conducted in real time and reduces the expense of the circuitry required.
摘要翻译：本发明解决了用于微调VCDL延迟线输出时钟的受控时钟源的产生。在这个修整过程中，对这些输出时钟的静态变化进行调整。本发明使用受控的时钟源消除了对该修整过程的实时性的需要，并且降低了所需电路的费用。

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