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81. 发明申请

US20120187490A1 FET STRUCTURES WITH TRENCH IMPLANTATION TO IMPROVE BACK CHANNEL LEAKAGE AND BODY RESISTANCE 有权
标题翻译：具有TRENCH植入的FET结构以提高反向通道泄漏和体电阻
公开(公告)号：US20120187490A1
公开(公告)日：2012-07-26
申请号：US13426547
申请日：2012-03-21
申请人： David M. Fried , Jeffrey B. Johnson , Kevin McStay , Paul C. Parries , Chengwen Pei , Gan Wang , Geng Wang , Yanli Zhang
发明人： David M. Fried , Jeffrey B. Johnson , Kevin McStay , Paul C. Parries , Chengwen Pei , Gan Wang , Geng Wang , Yanli Zhang
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L21/26586 , H01L27/1203 , H01L29/1083 , H01L29/165 , H01L29/66636 , H01L29/7833
摘要： A field effect transistor (FET) structure on a semiconductor substrate which includes a gate structure having a spacer on a semiconductor substrate; an extension implant underneath the gate structure; a recessed source and a recessed drain filled with a doped epitaxial material; halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack. In an exemplary embodiment, there is implanted junction butting underneath the bottom of each of the recessed source and drain, the junction butting being separate and distinct from the halo implanted regions. In another exemplary embodiment, the doped epitaxial material is graded from a lower dopant concentration at a side of the recessed source and drain to a higher dopant concentration at a center of the recessed source and drain. In a further exemplary embodiment, the semiconductor substrate is a semiconductor on insulator substrate.
摘要翻译：一种半导体衬底上的场效应晶体管（FET）结构，其包括在半导体衬底上具有间隔物的栅极结构; 栅极结构下面的延伸植入物; 凹陷的源极和填充有掺杂的外延材料的凹陷的漏极; 邻近凹陷源的底部的卤素注入区域和漏极并位于栅极叠层下方。在示例性实施例中，在凹陷源和漏极中的每一个的底部下方注入结合对接，该接合部分与光晕注入区域分开且不同。在另一个示例性实施例中，掺杂的外延材料从凹陷源的一侧的较低掺杂剂浓度和漏极分级到凹陷源极和漏极的中心处的较高掺杂剂浓度。在另一示例性实施例中，半导体衬底是绝缘体上半导体衬底。

82. 发明申请

US20110309474A1 TRENCH CAPACITOR 失效
标题翻译： TRENCH电容器
公开(公告)号：US20110309474A1
公开(公告)日：2011-12-22
申请号：US12818448
申请日：2010-06-18
申请人： Chengwen Pei , Xi Li , Geng Wang
发明人： Chengwen Pei , Xi Li , Geng Wang
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L29/945 , H01L21/3065 , H01L27/1087 , H01L29/36 , H01L29/66181
摘要： A trench and method of fabrication is disclosed. The trench shape is cylindrosymmetric, and is created by forming a dopant profile that is monotonically increasing in dopant concentration level as a function of depth into the substrate. A dopant sensitive etch is then performed, resulting in a trench shape providing increased surface area, yet having relatively smooth trench walls.
摘要翻译：公开了一种沟槽和制造方法。沟槽形状是圆柱对称的，并且通过形成掺杂剂分布而形成，掺杂剂分布随掺杂剂浓度水平而单调增加，作为进入衬底的深度的函数。然后进行掺杂剂敏感蚀刻，导致沟槽形状提供增加的表面积，但具有相对平滑的沟槽壁。

83. 发明申请

US20130032859A1 EPITAXIAL EXTENSION CMOS TRANSISTOR 有权
标题翻译：外延扩展CMOS晶体管
公开(公告)号：US20130032859A1
公开(公告)日：2013-02-07
申请号：US13198152
申请日：2011-08-04
申请人： Chengwen Pei , Geng Wang , Yanli Zhang
发明人： Chengwen Pei , Geng Wang , Yanli Zhang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6656 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/66628 , H01L29/66636
摘要： A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over expitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein.
摘要翻译：通过在半导体层上形成围绕栅极结构的第一深度的一对第一沟槽，在半导体层中形成一对水平台阶包含的沟槽，在栅极结构周围形成一次性间隔物，以覆盖第一并且通过形成大于第一深度的第二深度的一对第二沟槽。去除一次性间隔物，并进行选择性外延以形成集成的外延源和源极延伸区域以及集成的外延漏极和漏极延伸区域。可以在平坦化介电层的沉积和平坦化之后形成替代栅极结构，并且随后去除栅极结构并且在外延源极和漏极延伸区域上横向扩展栅极腔。或者，可以将接触电介质层直接沉积在集成的外延区上，并且可以在其中形成接触通孔结构。

84. 发明申请

US20120286392A1 SUPPRESSION OF DIFFUSION IN EPITAXIAL BURIED PLATE FOR DEEP TRENCHES 失效
标题翻译：抑制深海IN IN。ED。。。。。。。。。。。。。。。
公开(公告)号：US20120286392A1
公开(公告)日：2012-11-15
申请号：US13106349
申请日：2011-05-12
申请人： Chengwen Pei , Geng Wang
发明人： Chengwen Pei , Geng Wang
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L29/66181 , H01L21/2652 , H01L27/10829 , H01L27/10861 , H01L27/10897 , H01L29/945
摘要： Dopants of a first conductivity type are implanted into a top portion of a semiconductor substrate having a doping of the first conductivity type to increase the dopant concentration in the top portion, which is a first-conductivity-type semiconductor layer. A semiconductor material layer having a doping of the second conductivity type, a buried insulator layer, and a top semiconductor layer are formed thereupon. Deep trenches having a narrow width have a bottom surface within the second-conductivity-type semiconductor layer, which functions as a buried plate. Deep trenches having a wider width are etched into the first-conductivity-type layer underneath, and can be used to form an isolation structure. The additional dopants in the first-conductivity-type semiconductor layer provide a counterdoping against downward diffusion of dopants of the second conductivity type to enhance electrical isolation.
摘要翻译：将第一导电类型的掺杂剂注入到具有第一导电类型的掺杂的半导体衬底的顶部中，以增加作为第一导电型半导体层的顶部中的掺杂剂浓度。在其上形成具有第二导电类型的掺杂的半导体材料层，掩埋绝缘体层和顶部半导体层。具有窄宽度的深沟槽具有在第二导电型半导体层内的底表面，其用作掩埋板。具有较宽宽度的深沟槽被蚀刻到下面的第一导电类型层中，并且可用于形成隔离结构。第一导电型半导体层中的附加掺杂剂提供反向掺杂以抵抗第二导电类型的掺杂剂的向下扩散以增强电隔离。

85. 发明申请

US20120086077A1 FET STRUCTURES WITH TRENCH IMPLANTATION TO IMPROVE BACK CHANNEL LEAKAGE AND BODY RESISTANCE 有权
标题翻译：具有TRENCH植入的FET结构以提高反向通道泄漏和体电阻
公开(公告)号：US20120086077A1
公开(公告)日：2012-04-12
申请号：US12899635
申请日：2010-10-07
申请人： DAVID M FRIED , Jeffrey B. Johnson , Kevin McStay , Paul C. Parries , Chengwen Pei , Gan Wang , Geng Wang , Yanli Zhang
发明人： DAVID M FRIED , Jeffrey B. Johnson , Kevin McStay , Paul C. Parries , Chengwen Pei , Gan Wang , Geng Wang , Yanli Zhang
IPC分类号： H01L29/06 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/26586 , H01L27/1203 , H01L29/1083 , H01L29/165 , H01L29/66636 , H01L29/7833
摘要： An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage.
摘要翻译：半导体衬底上的FET结构，其包括在半导体衬底上形成用于栅极结构的源极和漏极的凹槽，通过源极和漏极凹部的底部的晕圈注入区域，位于栅极叠层下方的晕圈注入区域，注入在源极和漏极凹部的底部接合，并且用掺杂的外延材料填充源极和漏极凹部。在示例性实施例中，半导体衬底是在掩埋氧化物层上包括半导体层的绝缘体上半导体衬底。在示例性实施例中，接合对接和晕圈注入区域与掩埋氧化物层接触。在其他示例性实施例中，没有接合对接。在示例性实施例中，注入到栅极结构下面的FET体的下部的卤素注入在FET体的下部提供更高的掺杂水平，以降低体电阻，而不会干扰FET阈值电压。

86. 发明授权

US08642423B2 Polysilicon/metal contact resistance in deep trench 有权
公开(公告)号：US08642423B2
公开(公告)日：2014-02-04
申请号：US13307874
申请日：2011-11-30
申请人： Brian W. Messenger , Paul C. Parries , Chengwen Pei , Geng Wang , Yanli Zhang
发明人： Brian W. Messenger , Paul C. Parries , Chengwen Pei , Geng Wang , Yanli Zhang
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L27/10829 , H01L21/76898 , H01L21/84 , H01L23/481 , H01L27/1087 , H01L27/1203 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.

87. 发明授权

US08455327B2 Trench capacitor with spacer-less fabrication process 失效
公开(公告)号：US08455327B2
公开(公告)日：2013-06-04
申请号：US13198100
申请日：2011-08-04
申请人： Chengwen Pei , Xi Li , Geng Wang
发明人： Chengwen Pei , Xi Li , Geng Wang
IPC分类号： H01L21/20
CPC分类号： H01L29/0692 , H01L21/3081 , H01L21/3086 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L29/66181 , H01L29/945
摘要： A trench capacitor and method of fabrication are disclosed. The SOI region is doped such that a selective isotropic etch used for trench widening does not cause appreciable pullback of the SOI region, and no spacers are needed in the upper portion of the trench.

88. 发明申请

US20130134490A1 LOW RESISTANCE EMBEDDED STRAP FOR A TRENCH CAPACITOR 有权
公开(公告)号：US20130134490A1
公开(公告)日：2013-05-30
申请号：US13307787
申请日：2011-11-30
申请人： Karen A. Nummy , Chengwen Pei , Werner A. Rausch , Geng Wang
发明人： Karen A. Nummy , Chengwen Pei , Werner A. Rausch , Geng Wang
IPC分类号： H01L29/94 , H01L21/8242
CPC分类号： H01L21/4846 , H01L21/82 , H01L27/10867 , H01L29/66181 , H01L29/66636 , H01L29/945
摘要： A trench is formed in a semiconductor substrate, and is filled with a node dielectric layer and at least one conductive material fill portion that functions as an inner electrode. The at least one conductive material fill portion includes a doped polycrystalline semiconductor fill portion. A gate stack for an access transistor is formed on the semiconductor substrate, and a gate spacer is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion. An epitaxial source region and a polycrystalline semiconductor material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other without a gap therebetween. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode.

89. 发明申请

US20110272702A1 ENHANCED CAPACITANCE DEEP TRENCH CAPACITOR FOR EDRAM 有权
标题翻译： EDRAM的增强电容深度电容器
公开(公告)号：US20110272702A1
公开(公告)日：2011-11-10
申请号：US12775532
申请日：2010-05-07
申请人： Oh-jung Kwon , Junedong Lee , Chengwen Pei , Geng Wang
发明人： Oh-jung Kwon , Junedong Lee , Chengwen Pei , Geng Wang
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L28/82 , H01L27/10867 , H01L29/66181
摘要： A substrate including a stack of a handle substrate, an optional lower insulator layer, a doped polycrystalline semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. A deep trench is formed through the top semiconductor layer, the upper insulator layer, and the doped polycrystalline semiconductor layer. Exposed vertical surfaces of the polycrystalline semiconductor layer are crystallographically etched to form random facets in the deep trench, thereby increasing the total exposed surface area of the polycrystalline semiconductor layer in the deep trench. A node dielectric and at least one conductive material are deposited to fill the trench and to form a buried strap portion, which constitute a capacitor of an eDRAM. Access transistors and other logic devices can be formed.
摘要翻译：提供了包括手柄衬底，可选的下绝缘体层，掺杂多晶半导体层，上绝缘体层和顶部半导体层的衬底的衬底。通过顶部半导体层，上部绝缘体层和掺杂多晶半导体层形成深沟槽。多晶半导体层的暴露的垂直表面被晶体学蚀刻以在深沟槽中形成随机刻面，从而增加深沟槽中的多晶半导体层的总暴露表面积。沉积节点电介质和至少一种导电材料以填充沟槽并形成构成eDRAM的电容器的掩埋带部分。可以形成存取晶体管和其它逻辑器件。

90. 发明授权

US08592266B2 Replacement gate MOSFET with a high performance gate electrode 有权
公开(公告)号：US08592266B2
公开(公告)日：2013-11-26
申请号：US12912963
申请日：2010-10-27
申请人： Zhengwen Li , Dechao Guo , Randolph F. Knarr , Chengwen Pei , Gan Wang , Yanfeng Wang , Keith Kwong Hon Wong , Jian Yu , Jun Yuan
发明人： Zhengwen Li , Dechao Guo , Randolph F. Knarr , Chengwen Pei , Gan Wang , Yanfeng Wang , Keith Kwong Hon Wong , Jian Yu , Jun Yuan
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/42368 , H01L29/42376 , H01L29/49 , H01L29/66545 , H01L29/6659 , H01L29/66606 , H01L29/78 , H01L29/7833
摘要： In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

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