专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US06418051B2 Non-volatile memory device with configurable row redundancy 有权
公开(公告)号：US06418051B2
公开(公告)日：2002-07-09
申请号：US09785079
申请日：2001-02-14
申请人： Alessandro Manstretta , Rino Micheloni , Andrea Pierin , Emilio Yero
发明人： Alessandro Manstretta , Rino Micheloni , Andrea Pierin , Emilio Yero
IPC分类号： G11C1606
CPC分类号： G11C29/70
摘要： A non-volatile memory device with configurable row redundancy includes a non-volatile memory having a matrix of memory cells and a matrix of redundant memory cells, both organized into rows and columns. The memory device also includes row and column decoding circuits; read and modify circuits for reading and modifying data stored in the memory cells; and at least one associative memory matrix, also organized into rows and columns, able to store the addresses of faulty rows, and control circuits for controlling the associative memory matrix. The memory device further includes a circuit for recognizing and comparing selected row addresses with faulty row addresses contained in the associative memory matrix, such as to produce de-selection of the faulty row and selection of the corresponding redundant cell row in the event of a valid recognition; and a configuration register, also comprising a matrix of non-volatile memory cells, and associated control circuits.

82. 发明授权

US06373780B1 Single supply voltage nonvolatile memory device with row decoding 有权
标题翻译：单电源电压非易失性存储器件，具有行解码功能
公开(公告)号：US06373780B1
公开(公告)日：2002-04-16
申请号：US09627273
申请日：2000-07-28
申请人： Rino Micheloni , Osama Khouri , Andrea Sacco , Massimiliano Picca
发明人： Rino Micheloni , Osama Khouri , Andrea Sacco , Massimiliano Picca
IPC分类号： G11C800
CPC分类号： G11C5/145 , G11C5/14 , G11C8/10
摘要： The memory device comprises a memory array having an organization of the type comprising global word lines and local word lines, a global row decoder addressing the global word lines, a local row decoder addressing the local word lines, a global power supply stage supplying the global row decoder, and a local power supply stage supplying the local row decoder.
摘要翻译：存储器件包括具有包括全局字线和本地字线的组织的存储器阵列，寻址全局字线的全局行解码器，寻址本地字线的本地行解码器，提供全局字线的全局电源级行解码器，以及供应本地行解码器的本地电源级。

83. 发明授权

US06307396B1 Low-consumption TTL-CMOS input buffer stage 失效
标题翻译：低功耗TTL-CMOS输入缓冲级
公开(公告)号：US06307396B1
公开(公告)日：2001-10-23
申请号：US09231130
申请日：1998-12-30
申请人： Jacopo Mulatti , Marco Maccarrone , Ignazio Martines , Rino Micheloni
发明人： Jacopo Mulatti , Marco Maccarrone , Ignazio Martines , Rino Micheloni
IPC分类号： H03K190185
CPC分类号： H03K19/0016
摘要： A low-consumption TTL-CMOS input buffer stage includes a chain of inverters cascade connected between an input receiving electric signals at a TTL logic level and an output reproducing electric signals at a CMOS logic level, and powered between a first or supply voltage reference and a second or ground reference. Advantageously, the first inverter in the chain includes a means of selecting the delivery path to the stage according to an activate signal for a low-consumption operation mode. In essence, the first inverter of the buffer has two signal paths: one for normal operation and the other for low consumption operation.
摘要翻译：低功耗TTL-CMOS输入缓冲级包括串联的反相器链，其串联在接收TTL逻辑电平的电信号的输入端和CMOS逻辑电平的输出再现电信号之间，并且在第一或电源电压基准和第二或地面参考。有利地，链中的第一反相器包括根据低功耗操作模式的激活信号选择到载物台的输送路径的装置。实质上，缓冲器的第一个反相器具有两个信号路径：一个用于正常操作，另一个用于低功耗操作。

84. 发明授权

US6094073A Line decoder for memory devices 有权
标题翻译：用于存储器件的线路解码器
公开(公告)号：US6094073A
公开(公告)日：2000-07-25
申请号：US432642
申请日：1999-11-02
申请人： Giovanni Campardo , Rino Micheloni , Stefano Commodaro
发明人： Giovanni Campardo , Rino Micheloni , Stefano Commodaro
IPC分类号： G11C8/10 , G11C16/12 , H03K19/082
CPC分类号： G11C8/10 , G11C16/12
摘要： The row decoder includes a predecoding stage supplied with row addresses and generating predecoding signals; and a final decoding stage, which, on the basis of the predecoding signals, drives the individual rows in the array. The predecoding stage includes a number of predecoding circuits presenting two parallel signal paths: a low-voltage path used in read mode, and a high-voltage path used in programming mode. A CMOS switch separates the two paths, is driven by high voltage via a voltage shifter in programming mode, and, being formed at predecoding level, involves no integration problems.
摘要翻译：行解码器包括提供有行地址并产生预解码信号的预解码级; 以及最终解码阶段，其基于预解码信号驱动阵列中的各行。预解码阶段包括多个预解码电路，其呈现两个并行信号路径：在读取模式中使用的低电压路径，以及在编程模式中使用的高压路径。 CMOS开关将两路径分开，通过编程模式下的电压转换器由高电压驱动，并且在预解码级别形成，不涉及集成问题。

85. 发明授权

US6075750A Method and circuit for generating an ATD signal to regulate the access to a non-volatile memory 有权
标题翻译：用于产生ATD信号以调节对非易失性存储器的访问的方法和电路
公开(公告)号：US6075750A
公开(公告)日：2000-06-13
申请号：US186497
申请日：1998-11-04
申请人： Giovanni Campardo , Rino Micheloni , Marco Maccarrone , Matteo Zammattio
发明人： Giovanni Campardo , Rino Micheloni , Marco Maccarrone , Matteo Zammattio
IPC分类号： G11C8/18 , G11C8/00
CPC分类号： G11C8/18
摘要： A method and a circuit generate a pulse synchronization signal (ATD) for timing the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells. The method consists of duplicating the ATD signal into at least one pair of signals and propagating such signals through separate parallel timing chains at the ends of which the ATD signal is reinstated, the chains being alternately active.
摘要翻译：一种方法和电路产生用于对半导体集成电子存储器件中的存储单元读取相位进行定时的脉冲同步信号（ATD）。在检测到存储器单元的多个地址输入端中的至少一个的逻辑状态的变化时产生脉冲信号（ATD）。该方法包括将ATD信号复制到至少一对信号中，并且通过在ATD信号被恢复的端部处的分离的并行定时链传播这样的信号，链条交替活跃。

86. 发明授权

US5886925A Read circuit and method for nonvolatile memory cells with an equalizing structure 失效
标题翻译：具有均衡结构的非易失性存储单元的读取电路和方法
公开(公告)号：US5886925A
公开(公告)日：1999-03-23
申请号：US877922
申请日：1997-06-18
申请人： Giovanni Campardo , Rino Micheloni , Marco Maccarrone
发明人： Giovanni Campardo , Rino Micheloni , Marco Maccarrone
IPC分类号： G11C16/28 , G11C16/06
CPC分类号： G11C16/28
摘要： The read circuit presents a current mirror circuit including a first and second load transistor interposed between the supply line and a respective first and second output node. The first output node is connected to a cell to be read, the second output node is connected to a generating stage generating a reference current having a predetermined characteristic, and the size of the second load transistor is N times greater than the first load transistor. To permit rapid cell reading even in the presence of low supply voltage and with no initial uncertainty, an equalizing circuit presents a current balancing branch connected between the first output node and ground for generating an equalizing current presenting a ratio of 1/N with the reference current to balance the circuit before commencing the reading.
摘要翻译：读取电路提供电流镜电路，其包括插入在电源线和相应的第一和第二输出节点之间的第一和第二负载晶体管。第一输出节点连接到要读取的单元，第二输出节点连接到产生具有预定特性的参考电流的发生级，并且第二负载晶体管的尺寸大于第一负载晶体管的N倍。为了即使在低电源电压并且没有初始不确定性的情况下也允许快速电池读取，均衡电路提供连接在第一输出节点和地之间的电流平衡支路，用于产生与参考值1 / N的比率的均衡电流电流在开始读数之前平衡电路。

87. 发明授权

US08572361B2 Configuration of a multilevel flash memory device 有权
标题翻译：配置多级闪存设备
公开(公告)号：US08572361B2
公开(公告)日：2013-10-29
申请号：US13048760
申请日：2011-03-15
申请人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
发明人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
IPC分类号： G06F9/24
CPC分类号： G11C11/5621 , G11C16/20
摘要： A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory. The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device. This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.
摘要翻译：多级闪存设备允许更快更有效地配置存储器设备的操作参数，以执行存储器的不同功能的算法。在测试期间识别存储器件的操作参数的最佳配置通过允许将配置位一次性处理成算法友好的数据来简化，该数据存储在嵌入式辅助随机存取存储器中，每次上电时存储设备。这通过执行存储在嵌入式微处理器的辅助只读存储器中的特定加电算法代码来完成。

88. 发明授权

US07937576B2 Configuration of a multi-level flash memory device 有权
标题翻译：配置多级闪存设备
公开(公告)号：US07937576B2
公开(公告)日：2011-05-03
申请号：US11460777
申请日：2006-07-28
申请人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
发明人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
IPC分类号： G06F9/24
CPC分类号： G11C11/5621 , G11C16/20
摘要： A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.
摘要翻译：多级闪存设备允许更快更有效地配置存储器设备的操作参数，以便执行存储器的不同功能算法。简化了测试过程中存储器件工作参数的最佳配置的识别通过在存储器件的每次上电时允许将配置位一次性处理成存储在嵌入式辅助随机存取存储器中的算法友好数据。这通过执行存储在存储器装置中的特定加电算法代码来完成嵌入式微处理器的辅助只读存储器。

89. 发明授权

US07889586B2 Circuit and method for retrieving data stored in semiconductor memory cells 有权
标题翻译：用于检索存储在半导体存储单元中的数据的电路和方法
公开(公告)号：US07889586B2
公开(公告)日：2011-02-15
申请号：US12248843
申请日：2008-10-09
申请人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Rino Micheloni
发明人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Rino Micheloni
IPC分类号： G11C7/04
CPC分类号： G11C11/5642 , G11C7/04 , G11C16/30
摘要： A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic.
摘要翻译：电路包括至少一个存储单元，适于根据其电特性的值存储数据，其根据第一变化规律表现出与温度的变化性; 提供电压发生器，用于产生要提供给所述至少一个存储单元的电压以检索存储在其中的数据，所述电压发生器包括适于使所产生的电压取值至少包括至少一组目标值的值的第一装置一个目标值，对应于要在存储器单元上执行的操作。电压发生器包括第二装置，用于使得所产生的电压所采取的值根据规定的第二变化规律随温度变化，利用具有所述电特性的补偿电路元件。

90. 发明授权

US07349265B2 Reading method of a NAND-type memory device and NAND-type memory device 有权
标题翻译： NAND型存储器件和NAND型存储器件的读取方法
公开(公告)号：US07349265B2
公开(公告)日：2008-03-25
申请号：US11458916
申请日：2006-07-20
申请人： Luca Crippa , Chiara Missiroli , Rino Micheloni
发明人： Luca Crippa , Chiara Missiroli , Rino Micheloni
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/26
摘要： A reading method of a NAND memory device includes the steps of first connecting a first end terminal of a stack of cells to a reference line, second connecting a second end terminal of the stack of cells to a respective bitline, and charging the bitline to a predetermined bitline read voltage, where one of the steps of first connecting and second connecting is carried out before charging the bitline and the other of the steps of first connecting and second connecting is carried out after charging the bitline. An order of carrying out the steps of first connecting and second connecting is determined based on an address of a selected cell.
摘要翻译： NAND存储器件的读取方法包括以下步骤：首先将单元堆叠的第一端子连接到参考线，然后将单元堆叠的第二端子连接到相应的位线，以及将位线充电到预定的位线读取电压，其中在对位线充电之前执行第一连接和第二连接的步骤之一，并且在对位线充电之后执行第一连接和第二连接的另一个步骤。基于所选择的单元的地址来确定执行第一连接和第二连接的步骤的顺序。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式