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81. 发明授权

US08966335B2 Method for performing error corrections of digital information codified as a symbol sequence 有权
标题翻译：用于执行编码为符号序列的数字信息的纠错的方法
公开(公告)号：US08966335B2
公开(公告)日：2015-02-24
申请号：US12001294
申请日：2007-12-10
申请人： Massimiliano Lunelli , Rino Micheloni , Roberto Ravasio , Alessia Marelli
发明人： Massimiliano Lunelli , Rino Micheloni , Roberto Ravasio , Alessia Marelli
IPC分类号： H03M13/00 , H03M13/19 , H03M13/13 , H03M13/15
CPC分类号： H03M13/1575 , H03M13/13 , H03M13/15 , H03M13/19
摘要： A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to these systems is described, provides the transmission of sequences incorporating a portion of error corrector code allowing the sequence which is more probably the original transmitted through the calculation of an error syndrome using a parity matrix to be restored when received. Advantageously according to embodiments of the invention, the error code incorporated in the original sequence belongs to a non Boolean group.
摘要翻译：描述了一种用于对编码为符号序列的数字信息进行纠错的方法和系统，例如存储在电子存储器系统中或从这些系统发送的数字信息或从这些系统发送和传送到这些系统的数字信息，提供包含一部分误差校正码的序列的传输，这更可能是通过使用在接收时要恢复的奇偶校验矩阵的误差校正子的计算来传送的。有利地，根据本发明的实施例，并入原始序列中的错误代码属于非布尔组。

82. 发明授权

US08707122B1 Nonvolatile memory controller with two-stage error correction technique for enhanced reliability 有权
标题翻译：具有两级纠错技术的非易失性存储器控制器，增强可靠性
公开(公告)号：US08707122B1
公开(公告)日：2014-04-22
申请号：US13023336
申请日：2011-02-08
申请人： Rino Micheloni , Peter Z. Onufryk , Alessia Marelli , Christopher I. W. Norrie
发明人： Rino Micheloni , Peter Z. Onufryk , Alessia Marelli , Christopher I. W. Norrie
IPC分类号： H03M13/00
CPC分类号： H03M13/2915 , G06F11/1012 , G06F11/108 , H03M13/098 , H03M13/152
摘要： A nonvolatile memory controller generates an error correction code for each data unit in a data stripe and generates a parity unit based on the data units of the data stripe. If a data unit of the data stripe has a number of data bit errors not exceeding the error correction capacity of the nonvolatile memory controller, the nonvolatile memory controller corrects any data bit errors in the data unit based on the error correction code of the data unit. Otherwise, if a data unit of the data stripe has a number of data bit error exceeding the error correction capacity of the nonvolatile memory controller, the nonvolatile memory controller recovers the data unit based on the other data units of the data stripe and the parity unit.
摘要翻译：非易失性存储器控制器为数据条带中的每个数据单元生成纠错码，并且基于数据条带的数据单位生成奇偶校验单元。如果数据条带的数据单元具有不超过非易失性存储器控制器的纠错能力的多个数据位错误，则非易失性存储器控制器基于数据单元的纠错码来校正数据单元中的任何数据位错误。否则，如果数据条带的数据单元具有超过非易失性存储器控制器的纠错能力的数据位错误数，则非易失性存储器控制器基于数据条带和奇偶校验单元的其他数据单元来恢复数据单元。

83. 发明授权

US08656257B1 Nonvolatile memory controller with concatenated error correction codes 有权
标题翻译：具有级联纠错码的非易失性存储器控制器
公开(公告)号：US08656257B1
公开(公告)日：2014-02-18
申请号：US13434770
申请日：2012-03-29
申请人： Rino Micheloni , Alessia Marelli , Peter Z. Onufryk , Christopher I. W. Norrie
发明人： Rino Micheloni , Alessia Marelli , Peter Z. Onufryk , Christopher I. W. Norrie
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： H03M13/3707 , G06F11/1012 , G06F11/108 , G06F2211/109 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/152 , H03M13/2906
摘要： A nonvolatile memory controller may recover encoded data using the outer error correction code of the encoded data if it is determined that a correction capacity of the outer error correction code is not exceeded. Alternatively, the nonvolatile memory controller may recover the encoded data using the inner error correction code of the encoded data followed by the outer error correction code of the encoded data if it is determined that the correction capacity of the outer error correction code is exceeded. Additionally, if it is determined that the correction capacity of the outer error correction code is exceed after recovering the data using the inner error correction code, the nonvolatile memory storage module may perform a redundant array of independent disks (RAID) operation to recover the data.
摘要翻译：如果确定不超过外部纠错码的校正容量，则非易失性存储器控制器可以使用编码数据的外部纠错码来恢复编码数据。或者，如果确定超出了外部纠错码的校正容量，则非易失性存储器控制器可以使用编码数据的内部纠错码来跟踪编码数据的外部纠错码来恢复编码数据。此外，如果在使用内部纠错码恢复数据之后确定外部纠错码的校正能力超过，则非易失性存储器存储模块可以执行独立盘（RAID）冗余阵列操作以恢复数据。

84. 发明授权

US08572361B2 Configuration of a multilevel flash memory device 有权
标题翻译：配置多级闪存设备
公开(公告)号：US08572361B2
公开(公告)日：2013-10-29
申请号：US13048760
申请日：2011-03-15
申请人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
发明人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
IPC分类号： G06F9/24
CPC分类号： G11C11/5621 , G11C16/20
摘要： A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory. The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device. This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.
摘要翻译：多级闪存设备允许更快更有效地配置存储器设备的操作参数，以执行存储器的不同功能的算法。在测试期间识别存储器件的操作参数的最佳配置通过允许将配置位一次性处理成算法友好的数据来简化，该数据存储在嵌入式辅助随机存取存储器中，每次上电时存储设备。这通过执行存储在嵌入式微处理器的辅助只读存储器中的特定加电算法代码来完成。

85. 发明授权

US08347201B2 Reading method of a memory device with embedded error-correcting code and memory device with embedded error-correcting code 有权
标题翻译：具有嵌入式纠错码的存储器件的读取方法和具有嵌入式纠错码的存储器件
公开(公告)号：US08347201B2
公开(公告)日：2013-01-01
申请号：US13047678
申请日：2011-03-14
申请人： Alessia Marelli , Valeria Intini , Roberto Ravasio , Rino Micheloni
发明人： Alessia Marelli , Valeria Intini , Roberto Ravasio , Rino Micheloni
IPC分类号： G06F7/02 , H03M13/00
CPC分类号： G06F11/1076 , G06F11/1068 , G06F11/141 , G11B20/18
摘要： A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A0, A1, . . . , ALS-1) to generate a first recovered string (S1), and performing a first decoding attempt using the first recovered string (S1). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S2-SN) is generated. On the basis of a comparison between the first recovered string (S1) and the second recovered string (S2-SN), a modified string (SM) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (SM).
摘要翻译：具有纠错编码的存储器件的读取方法设想的步骤是：执行多个存储器位置（A0，A1，...，ALS-1）的第一读取以产生第一恢复串（S1），并且使用第一恢复串执行第一解码尝试（S1）。当第一解码尝试失败时，至少读取一次存储器位置，并产生至少一个第二恢复字符串（S2-SN）。基于第一恢复串（S1）和第二恢复串（S2-SN）之间的比较，生成修改串（SM），其中存在擦除（X），并且至少一个第二解码尝试使用修改后的字符串（SM）进行。

86. 发明授权

US07937576B2 Configuration of a multi-level flash memory device 有权
标题翻译：配置多级闪存设备
公开(公告)号：US07937576B2
公开(公告)日：2011-05-03
申请号：US11460777
申请日：2006-07-28
申请人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
发明人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
IPC分类号： G06F9/24
CPC分类号： G11C11/5621 , G11C16/20
摘要： A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.
摘要翻译：多级闪存设备允许更快更有效地配置存储器设备的操作参数，以便执行存储器的不同功能算法。简化了测试过程中存储器件工作参数的最佳配置的识别通过在存储器件的每次上电时允许将配置位一次性处理成存储在嵌入式辅助随机存取存储器中的算法友好数据。这通过执行存储在存储器装置中的特定加电算法代码来完成嵌入式微处理器的辅助只读存储器。

87. 发明授权

US07908543B2 Reading method of a memory device with embedded error-correcting code and memory device with embedded error-correcting code 有权
标题翻译：具有嵌入式纠错码的存储器件的读取方法和具有嵌入式纠错码的存储器件
公开(公告)号：US07908543B2
公开(公告)日：2011-03-15
申请号：US11713376
申请日：2007-03-01
申请人： Alessia Marelli , Valeria Intini , Roberto Ravasio , Rino Micheloni
发明人： Alessia Marelli , Valeria Intini , Roberto Ravasio , Rino Micheloni
IPC分类号： H03M13/00
CPC分类号： G06F11/1076 , G06F11/1068 , G06F11/141 , G11B20/18
摘要： A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A0, A1, . . . , ALS−1) to generate a first recovered string (S1), and performing a first decoding attempt using the first recovered string (S1). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S2-SN) is generated. On the basis of a comparison between the first recovered string (S1) and the second recovered string (S2-SN), a modified string (SM) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (SM).
摘要翻译：具有纠错编码的存储器件的读取方法设想的步骤是：执行多个存储器位置（A0，A1，...，ALS-1）的第一读取以产生第一恢复串（S1），并且使用第一恢复串执行第一解码尝试（S1）。当第一解码尝试失败时，至少读取一次存储器位置，并产生至少一个第二恢复字符串（S2-SN）。基于第一恢复串（S1）和第二恢复串（S2-SN）之间的比较，生成修改串（SM），其中存在擦除（X），并且至少一个第二解码尝试使用修改后的字符串（SM）进行。

88. 发明授权

US07889586B2 Circuit and method for retrieving data stored in semiconductor memory cells 有权
标题翻译：用于检索存储在半导体存储单元中的数据的电路和方法
公开(公告)号：US07889586B2
公开(公告)日：2011-02-15
申请号：US12248843
申请日：2008-10-09
申请人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Rino Micheloni
发明人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Rino Micheloni
IPC分类号： G11C7/04
CPC分类号： G11C11/5642 , G11C7/04 , G11C16/30
摘要： A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic.
摘要翻译：电路包括至少一个存储单元，适于根据其电特性的值存储数据，其根据第一变化规律表现出与温度的变化性; 提供电压发生器，用于产生要提供给所述至少一个存储单元的电压以检索存储在其中的数据，所述电压发生器包括适于使所产生的电压取值至少包括至少一组目标值的值的第一装置一个目标值，对应于要在存储器单元上执行的操作。电压发生器包括第二装置，用于使得所产生的电压所采取的值根据规定的第二变化规律随温度变化，利用具有所述电特性的补偿电路元件。

89. 发明授权

US07349265B2 Reading method of a NAND-type memory device and NAND-type memory device 有权
标题翻译： NAND型存储器件和NAND型存储器件的读取方法
公开(公告)号：US07349265B2
公开(公告)日：2008-03-25
申请号：US11458916
申请日：2006-07-20
申请人： Luca Crippa , Chiara Missiroli , Rino Micheloni
发明人： Luca Crippa , Chiara Missiroli , Rino Micheloni
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/26
摘要： A reading method of a NAND memory device includes the steps of first connecting a first end terminal of a stack of cells to a reference line, second connecting a second end terminal of the stack of cells to a respective bitline, and charging the bitline to a predetermined bitline read voltage, where one of the steps of first connecting and second connecting is carried out before charging the bitline and the other of the steps of first connecting and second connecting is carried out after charging the bitline. An order of carrying out the steps of first connecting and second connecting is determined based on an address of a selected cell.
摘要翻译： NAND存储器件的读取方法包括以下步骤：首先将单元堆叠的第一端子连接到参考线，然后将单元堆叠的第二端子连接到相应的位线，以及将位线充电到预定的位线读取电压，其中在对位线充电之前执行第一连接和第二连接的步骤之一，并且在对位线充电之后执行第一连接和第二连接的另一个步骤。基于所选择的单元的地址来确定执行第一连接和第二连接的步骤的顺序。

90. 发明申请

US20080065937A1 NAND FLASH MEMORY DEVICE WITH ECC PROTECTED RESERVED AREA FOR NON-VOLATILE STORAGE OF REDUNDANCY DATA 审中-公开
标题翻译：具有ECC保护区域的NAND闪存存储器件，用于非易失存储冗余数据
公开(公告)号：US20080065937A1
公开(公告)日：2008-03-13
申请号：US11854685
申请日：2007-09-13
申请人： Rino Micheloni , Roberto Ravasio , Alessia Marelli
发明人： Rino Micheloni , Roberto Ravasio , Alessia Marelli
IPC分类号： G11C29/04
CPC分类号： G11C29/82 , G06F11/1068 , G11C29/24 , G11C2029/0411
摘要： Basic redundancy information is non-volatily stored in a reserved area of an addressable area of a memory array, and is copied to volatile storage therein at every power-on of the memory device. The unpredictable though statistically inevitable presence of failed array elements in such a reserved area of the memory array corrupts the basic redundancy information established during the test-on wafer (EWS) phase of the fabrication process. This increases the number of rejects, and lowers the yield of the fabrication process. This problem is addressed by writing the basic redundancy data in the reserved area of the array with an ECC technique using a certain error correction code. The error correction code may be chosen among majority codes 3, 5, 7, 15 and the like, or the Hamming code for 1, 2, 3 or more errors, as a function of the fail probability of a memory cell as determined by the EWS phase during fabrication.
摘要翻译：基本冗余信息被非挥发地存储在存储器阵列的可寻址区域的保留区域中，并且在存储器件的每次上电时复制到其中的易失性存储器。在存储器阵列的这种保留区域中，不可预测的，不可避免的存在故障阵列元件会破坏在制造过程的测试晶片（EWS）阶段期间建立的基本冗余信息。这增加了废品的数量，降低了制造工艺的产量。通过使用特定的纠错码通过ECC技术将阵列的保留区域中的基本冗余数据写入该问题来解决该问题。可以在多数代码3,5,7,15等之中选择纠错码，或者对于1,2,3或更多个错误，可以选择Hamming代码作为存储器单元的故障概率的函数，如由 EWS相制造期间。

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