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81. 发明授权

US06961875B2 Method and apparatus for capturing event traces for debug and analysis 失效
标题翻译：捕获事件跟踪的方法和装置，用于调试和分析
公开(公告)号：US06961875B2
公开(公告)日：2005-11-01
申请号：US09815548
申请日：2001-03-22
申请人： Michael Stephen Floyd , Balaram Sinharoy
发明人： Michael Stephen Floyd , Balaram Sinharoy
IPC分类号： G06F9/44 , G06F11/00 , G06F11/36
CPC分类号： G06F11/3636
摘要： A trace array having M entries with corresponding M addresses is used to store the states of input signals. The M addresses of the trace array are sequenced with a counter that counts a clock beginning at a starting count and counting to an ending count. If the ending count is exceeded, the counter starts over at the starting count. The counter outputs are decoded to addresses of the trace array. An event signal is generated on the occurrence of an operation of interest and the counter is started and stopped in response to sequences of the event signals, thus starting and stopping the recording of states of the input signals in the trace array. When an error or particular condition signal occurs, traces corresponding to the input signals are saved in the trace array. A start signal enables tracing and event logic generates event sequence signals which alternately start and stop the recording of traces. The event sequences are programmed by inputs to enable guaranteed statistical chances of capturing states of the input signals corresponding to a particular event signal occurring before an error or another event signal.
摘要翻译：使用具有对应M地址的M个条目的跟踪数组来存储输入信号的状态。跟踪数组的M地址用计数器计数，该计数器从起始计数开始计数一个时钟，并计数到结束计数。如果超出结束计数，则计数器从起始计数开始。计数器输出被解码为跟踪数组的地址。在感兴趣的操作的发生时产生事件信号，并且响应于事件信号的序列开始和停止计数器，从而启动和停止跟踪阵列中的输入信号的状态的记录。当发生错误或特定条件信号时，对应于输入信号的迹线将保存在跟踪数组中。起始信号使跟踪和事件逻辑产生交替地启动和停止记录记录的事件序列信号。事件序列由输入编程，以使保证的统计机会能够捕捉与在错误或其它事件信号之前发生的特定事件信号相对应的输入信号的状态。

82. 发明授权

US06823447B2 Software hint to improve the branch target prediction accuracy 失效
标题翻译：软件提示提高分支目标预测精度
公开(公告)号：US06823447B2
公开(公告)日：2004-11-23
申请号：US09798166
申请日：2001-03-01
申请人： Robert William Hay , Balaram Sinharoy
发明人： Robert William Hay , Balaram Sinharoy
IPC分类号： G06F900
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/3846
摘要： A field is defined in branch instructions which is interpreted by software as “Hint” bits and these bits are used to signal the processor of special circumstances that may arise when doing speculative branch instruction execution to enable better branch address prediction accuracy and a reduction in link stack corruption which improves overall execution times. A programmer or compiler determines if a branch instruction usage fits in the context for a Hint action. If so, the compiler or programmer, using assembly/machine language, sets Hint bits in the branch instruction when it is compiled. If the branch is later speculatively executed, the processor decodes the Hint bits and executes and a hardware action corresponding the decode of the Hint bits. These Hints include four specific Hint actions, however, the field reserved for Hint bits is five bit wide reserving up to thirty-two specific Hint cases may be specified. These Hint cases (or Hint bits) may be interpreted differently for each type of branch instruction supported.
摘要翻译：在分支指令中定义了一个字段，由软件将其解释为“提示”位，这些位用于向处理器发出信号，以便在进行推测性分支指令执行时可能出现的特殊情况，以实现更好的分支地址预测精度和减少链路堆栈损坏可以提高整体执行时间。程序员或编译器确定分支指令使用是否符合提示操作的上下文。如果是这样，编译器或程序员使用汇编/机器语言在编译时在转移指令中设置提示位。如果分支稍后被推测执行，则处理器对提示位进行解码并执行和与提示位的解码相对应的硬件动作。这些提示包括四个具体的提示操作，但是，为提示位保留的字段是五位宽保留，最多可以指定三十二个特定的提示情况。对于支持的每种类型的分支指令，可以对这些提示情况（或提示位）进行不同的解释。

83. 发明授权

US06598152B1 Increasing the overall prediction accuracy for multi-cycle branch prediction and apparatus by enabling quick recovery 有权
标题翻译：通过实现快速恢复，提高多周期分支预测和设备的总体预测精度
公开(公告)号：US06598152B1
公开(公告)日：2003-07-22
申请号：US09436264
申请日：1999-11-08
申请人： Balaram Sinharoy
发明人： Balaram Sinharoy
IPC分类号： G06F938
CPC分类号： G06F9/3861 , G06F9/3848
摘要： Enables a processor to quickly recover reliable use of a multi-cycle index used in a branch prediction mechanism for certain types of flush events occurring in the processor pipeline, whether the flush event occurs for a non-branch instruction or for a branch instruction contained in the same dispatch group. A GHV (global history vector) value is used in the generation of a multi-cycle index required for locating a prediction in a GBHT (global branch history table) for the instruction associated with the GHV value. The GHV value is captured in a BIQ (branch information queue) element representing each branch instruction selected for execution of a program. The BIQ element also captures an associated GHV count when the GHV value is captured. Recovery involves quickly restoring a GHV register to the captured GHV value when the GHV count captured in the same BIQ element has at least the value of N where N is the number contiguous fetch cycles without interruption required for the development of a steady state multi-cycle index value used in locating branch predictions in a global branch history table.
摘要翻译：使处理器可以快速恢复在分支预测机制中使用的多循环索引的可靠使用，用于在处理器流水线中发生的某些类型的刷新事件，无论是否为非分支指令或分支指令发生刷新事件相同的调度组。 GHV（全局历史向量）值用于生成与GHV值相关联的指令的GBHT（全局分支历史表）中的预测所需的多周期索引。 GHV值被捕获在表示为执行程序而选择的每个分支指令的BIQ（分支信息队列）元素中。当捕获GHV值时，BIQ元素还捕获相关的GHV计数。恢复涉及当在同一BIQ元件中捕获的GHV计数至少具有N值N时，快速将GHV寄存器恢复到所捕获的GHV值，其中N是连续获取周期数，而不需要中断开发稳态多周期用于在全局分支历史表中定位分支预测的索引值。

84. 发明授权

US06526503B1 Apparatus and method for accessing a memory device during speculative instruction branching 失效
标题翻译：在推测性指令分支期间访问存储器件的装置和方法
公开(公告)号：US06526503B1
公开(公告)日：2003-02-25
申请号：US09434763
申请日：1999-11-04
申请人： Balaram Sinharoy
发明人： Balaram Sinharoy
IPC分类号： G06F942
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/3863 , G06F9/4486
摘要： Instruction branching circuitry including a plurality of logical stacks each having a plurality of entries for storing an address for accessing a corresponding instruction in a memory device. A counter generates a pointer to an entry in an active one of the logical stacks, the counter including incrementation logic incrementing a stored pointer value following a Push operation and decrementation logic decrementing the stored pointer value following a Pop operation to the active one of the logical stacks. Selector circuitry selects the active one of the logical stacks in accordance with the performance of the Push and Pop operations.
摘要翻译：指令分支电路，其包括多个逻辑堆栈，每个逻辑堆栈具有多个条目，用于存储访问存储器设备中相应指令的地址。计数器产生指向逻辑堆栈中的活动的一个条目中的条目的指针，该计数器包括递增逻辑，其在按压操作之后增加存储的指针值，并且在弹出操作之后将存储的指针值递减到逻辑的活动的一个之后的递减逻辑堆栈选择器电路根据Push和Pop操作的性能选择活动的逻辑堆栈。

85. 发明授权

US09110885B2 Techniques for cache injection in a processor system 有权
标题翻译：在处理器系统中缓存注入的技术
公开(公告)号：US09110885B2
公开(公告)日：2015-08-18
申请号：US12212917
申请日：2008-09-18
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/00 , G06F13/28 , G06F12/08
CPC分类号： G06F13/28 , G06F12/0835 , G06F2212/507 , G06F2212/621
摘要： A technique for performing cache injection includes monitoring addresses on a bus. Ownership of input/output data on the bus is acquired by a cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache.
摘要翻译：执行高速缓存注入的技术包括监视总线上的地址。当总线上的地址（与输入/输出数据相关联）对应于存储在高速缓存中的数据块的地址时，通过高速缓存获取总线上的输入/输出数据的所有权。

86. 发明授权

US08949837B2 Assist thread for injecting cache memory in a microprocessor 有权
标题翻译：协助在微处理器中注入高速缓存的线程
公开(公告)号：US08949837B2
公开(公告)日：2015-02-03
申请号：US13434423
申请日：2012-03-29
申请人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
发明人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
IPC分类号： G06F9/46 , G06F12/00 , G06F9/38 , G06F12/08 , G06F9/48
CPC分类号： G06F9/383 , G06F9/3851 , G06F9/4881 , G06F12/0862
摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.
摘要翻译：数据处理系统包括具有访问多级缓存存储器的微处理器。微处理器执行从源代码对象编译的主线程。该系统包括用于执行也源自源代码对象的辅助线程的处理器。辅助线程包括主线程的存储器参考指令和仅解析存储器参考指令所需的算术指令。配置成与对应的执行线程一起调度辅助线程的调度器被配置为通过诸如主处理器周期的数量或代码指令的数量的可确定的阈值来执行执行线程之前的辅助线程。辅助线程可以在主处理器或专用辅助处理器中执行，该处理器直接对下一级高速缓冲存储器元件之一进行存储器访问。

87. 发明授权

US08904151B2 Method and apparatus for the dynamic identification and merging of instructions for execution on a wide datapath 有权
标题翻译：用于动态识别和合并用于在宽数据路径上执行的指令的方法和装置
公开(公告)号：US08904151B2
公开(公告)日：2014-12-02
申请号：US11416421
申请日：2006-05-02
申请人： Michael Gschwind , Balaram Sinharoy
发明人： Michael Gschwind , Balaram Sinharoy
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3853 , G06F9/30014 , G06F9/30036 , G06F9/30043 , G06F9/30112 , G06F9/3013 , G06F9/30149 , G06F9/3017 , G06F9/30196 , G06F9/382 , G06F9/384 , G06F9/3861
摘要： A processing system and method includes a predecoder configured to identify instructions that are combinable. Instruction storage is configured to merge instructions that are combinable by replacing the combinable instructions with a wide data internal instruction for execution. An instruction execution unit is configured to execute the internal instruction on a wide datapath.
摘要翻译：一种处理系统和方法包括：预解码器，被配置为识别可组合的指令。指令存储被配置为通过用可执行的宽数据内部指令替换可组合指令来合并可组合的指令。指令执行单元被配置为在宽数据路径上执行内部指令。

88. 发明授权

US08595443B2 Varying a data prefetch size based upon data usage 有权
标题翻译：基于数据使用改变数据预取大小
公开(公告)号：US08595443B2
公开(公告)日：2013-11-26
申请号：US12024163
申请日：2008-02-01
申请人： Ravi K. Arimilli , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A method of data processing in a processor includes maintaining a usage history indicating demand usage of prefetched data retrieved into cache memory. An amount of data to prefetch by a data prefetch request is selected based upon the usage history. The data prefetch request is transmitted to a memory hierarchy to prefetch the selected amount of data into cache memory.
摘要翻译：一种处理器中的数据处理方法，包括维护指示对高速缓存存储器检索的预取数据的需求使用的使用历史。基于使用历史来选择由数据预取请求预取的数据量。将数据预取请求发送到存储器层次结构，以将所选择的数据量预取到高速缓冲存储器中。

89. 发明授权

US08429349B2 Techniques for cache injection in a processor system with replacement policy position modification 失效
标题翻译：在具有替换政策位置修改的处理器系统中缓存注入的技术
公开(公告)号：US08429349B2
公开(公告)日：2013-04-23
申请号：US12212977
申请日：2008-09-18
申请人： Lakshminarayana Baba Arimilli , Ravi K. Arimilli , Balaram Sinharoy
发明人： Lakshminarayana Baba Arimilli , Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0862 , G06F12/0835 , G06F12/127 , G06F2212/6028
摘要： A technique for performing cache injection includes monitoring, at a cache, addresses on a bus. Ownership of input/output data on the bus is then acquired by the cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache. A replacement policy position of the data block is then modified (to increase a probability that the data block is consumed prior to ejection from the cache).
摘要翻译：用于执行高速缓存注入的技术包括在缓存上监视总线上的地址。当总线上的地址（与输入/输出数据相关联）对应于存储在高速缓存中的数据块的地址时，总线上的输入/输出数据的所有权由高速缓存获取。然后修改数据块的替换策略位置（以增加数据块在从高速缓存弹出之前消耗的概率）。

90. 发明授权

US08407680B2 Operand data structure for block computation 有权
标题翻译：块计算的操作数数据结构
公开(公告)号：US08407680B2
公开(公告)日：2013-03-26
申请号：US12336301
申请日：2008-12-16
申请人： Ravi K. Arimilli , Balaram Sinharoy
发明人： Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F9/45
CPC分类号： G06F8/4441 , G06F8/447
摘要： In response to receiving pre-processed code, a compiler identifies a code section that is not a candidate for acceleration and a code block that is a candidate for acceleration. The code block specifies an iterated operation having a first operand and a second operand, where each of multiple first operands and each of multiple second operands for the iterated operation has a defined addressing relationship. In response to the identifying, the compiler generates post-processed code containing lower level instruction(s) corresponding to the identified code section and creates and outputs an operand data structure separate from the post-processed code. The operand data structure specifies the defined addressing relationship for the multiple first operands and for the multiple second operands. The compiler places a block computation command in the post-processed code that invokes processing of the operand data structure to compute operand addresses.
摘要翻译：响应于接收预处理的代码，编译器识别不是加速候选的代码段和作为加速候选的代码块。代码块指定具有第一操作数和第二操作数的迭代操作，其中用于迭代操作的多个第一操作数和多个第二操作数中的每一个具有定义的寻址关系。响应于识别，编译器生成包含对应于所识别的代码段的较低级别指令的后处理代码，并创建并输出与后处理代码分离的操作数数据结构。操作数数据结构指定多个第一个操作数和多个第二个操作数的定义的寻址关系。编译器在后处理代码中放置块计算命令，该代码调用操作数数据结构的处理以计算操作数地址。

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