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81. 发明授权

US06178484B1 DCBST with ICBI mechanism to maintain coherency of bifurcated data and instruction caches 失效
标题翻译： DCBST与ICBI机制保持分叉数据和指令高速缓存的一致性
公开(公告)号：US06178484B1
公开(公告)日：2001-01-23
申请号：US09024585
申请日：1998-02-17
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/0811
摘要： Depending on a processor or instruction mode, a data cache block store (dcbst) or equivalent instruction is treated differently. A coherency maintenance mode for the instruction, in which the instruction is utilized to maintain coherency between bifurcated data and instruction caches, may be entered by setting bits in a processor register or by setting hint bits within the instruction. In the coherency maintenance mode, the instruction both pushes modified data to system memory and invalidates the cache entry in instruction caches. Subsequent instruction cache block invalidate (icbi) or equivalent instructions targeting the same cache location are no-oped when issued by a processor following a data cache block store or equivalent instruction executed in coherency maintenance mode. Execution of the data cache clock store instruction in coherency maintenance mode results in a novel system bus operation being initiated on the system bus. The bus operation directs other devices having bifurcated data and instruction caches to clean the specified cache entry in their data cache to at least the point of instruction/data cache coherency and invalidate the specified cache entry in their instruction cache. When repeatedly employed in sequence to write one or more pages of data to system memory, the mechanism for maintaining coherency saves processor cycles and reduces both address and data bus traffic.
摘要翻译：根据处理器或指令模式，数据高速缓存块存储（dcbst）或等效指令的处理方式不同。可以通过设置处理器寄存器中的位或通过在指令内设置提示位来输入用于指令用于维持分支数据和指令高速缓存之间的一致性的指令的一致性维护模式。在相干维护模式下，指令将修改的数据推送到系统存储器，并使指令高速缓存中的高速缓存条目无效。随后指令高速缓存块无效（icbi）或针对同一高速缓存位置的等效指令在由数据高速缓存块存储器执行的处理器发出或在相干性维护模式下执行的等效指令时不会执行。在一致性维护模式下执行数据高速缓存时钟存储指令导致在系统总线上启动新颖的系统总线操作。总线操作指示具有分叉数据和指令高速缓存的其他设备将其数据高速缓存中的指定高速缓存条目清理为至少指令/数据高速缓存一致性点，并使其指令高速缓存中指定的高速缓存条目无效。当重复按顺序将一个或多个数据页写入系统存储器时，用于维持一致性的机制节省了处理器周期，并减少了地址和数据总线流量。

82. 发明授权

US06173371B2 Demand-based issuance of cache operations to a processor bus 失效
标题翻译：基于需求的缓存操作向处理器总线发布
公开(公告)号：US06173371B2
公开(公告)日：2001-01-09
申请号：US08834113
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis , Derek Edward Williams
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis , Derek Edward Williams
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A method of managing and speculatively issuing architectural operations in a computer system. A first architectural operation is snooped and translated into a plurality of granular architectural operations to effect a large-scale architectural operation. The first architectural operation can be a first cache instruction directed to a memory block, and a plurality of cache instructions are issued which are directed to memory blocks contained in a page associated with the memory block. The granular architectural operations are transmitted to a processor bus of the computer system. A processor bus history table may be used to store a record of the large-scale architectural operation. The history table then can filter out any later architectural operation that is subsumed by the large-scale architectural operation. The history table monitors the processor bus to ensure that the large-scale architectural operations recorded in the table are still valid.
摘要翻译：一种在计算机系统中管理和推测性地发布架构操作的方法。第一个架构操作被窥探并转换成多个细粒度的架构操作，以实现大规模的架构操作。第一架构操作可以是针对存储器块的第一高速缓存指令，并且发出指向包含在与存储器块相关联的页面中的存储器块的多个高速缓存指令。粒度结构操作被传送到计算机系统的处理器总线。处理器总线历史表可以用于存储大型建筑操作的记录。历史表然后可以过滤掉大型建筑操作所包含的任何后来的建筑操作。历史表监视处理器总线，以确保表中记录的大型架构操作仍然有效。

83. 发明授权

US6138218A Forward progress on retried snoop hits by altering the coherency state of a local cache 失效
标题翻译：通过更改本地缓存的一致性状态来重试侦听命中的进展
公开(公告)号：US6138218A
公开(公告)日：2000-10-24
申请号：US24616
申请日：1998-02-17
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0833 , G06F12/0811
摘要： When a device snooping the system bus of a multiprocessor system detects an operation requesting data which is resident within a local memory in a coherency state requiring the data to be sourced from the device, the device attempts a intervention. If the intervention is impeded by a second device asserting a retry, the device sets a flag to provide historical information regarding the failed intervention. On a subsequent snoop hit to the same cache location, if the device again asserts an intervention and the snooped operation is again retried, the device undertakes an action to alter the coherency state of the requested cache item towards an ultimate coherency state expected to be the result of the original operation requesting the cache item. In the case where the requested cache item includes modified data resident in the device's local memory, the action may include a push operation writing the requested cache item to system memory. This operation may be snooped by other devices from the system bus to update their local memories. In the case where the requested cache item includes data in a coherency state other than the modified state, the action may include simply altering the coherency state to a shared or invalid state.
摘要翻译：当监视多处理器系统的系统总线的设备检测到需要数据来自设备的一致性状态下请求驻留在本地存储器内的数据的操作时，设备尝试干预。如果介入被第二个设备阻止重试，设备将设置一个标志来提供有关故障干预的历史信息。在随后的窥探命中到相同的高速缓存位置时，如果设备再次断言干预并且再次重试被窥探的操作，则设备进行动作以将所请求的高速缓存项目的一致性状态改变为预期为最终相关性的最终一致性状态请求缓存项目的原始操作的结果。在请求的高速缓存项目包括驻留在设备的本地存储器中的修改数据的情况下，该动作可以包括将所请求的高速缓存项目写入系统存储器的推送操作。该操作可能被其他设备从系统总线窥探以更新其本地存储器。在所请求的高速缓存项目包括除修改状态之外的一致性状态的数据的情况下，该动作可以包括简单地将一致性状态改变为共享状态或无效状态。

84. 发明授权

US6032226A Method and apparatus for layering cache and architectural specific functions to expedite multiple design 失效
标题翻译：用于分层缓存和架构特定功能的方法和装置，以加快多重设计
公开(公告)号：US6032226A
公开(公告)日：2000-02-29
申请号：US834115
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis , Derek Edward Williams
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis , Derek Edward Williams
IPC分类号： G06F12/08 , G06F12/00 , G06F13/00
CPC分类号： G06F12/0888
摘要： Cache and architectural specific functions within a cache controller are layered and provided with generic interfaces, isolating the complexities of each and allowing the overall functionality to be further divided into distinct, largely autonomous functional units. Each functional unit handles a certain type of operation and may be easily replicated or removed from the design to provide a number of cache designs with varied price and performance.
摘要翻译：高速缓存控制器中的缓存和架构特定功能被分层并提供通用接口，隔离每个接口的复杂性，并允许将整体功能进一步分为不同的，主要是自主的功能单元。每个功能单元处理某种类型的操作，并且可以容易地从设计中复制或移除，以提供具有不同价格和性能的多个高速缓存设计。

85. 发明授权

US6029204A Precise synchronization mechanism for SMP system buses using tagged snoop operations to avoid retries 失效
标题翻译： SMP系统总线的精确同步机制，使用标记的窥探操作来避免重试
公开(公告)号：US6029204A
公开(公告)日：2000-02-22
申请号：US815648
申请日：1997-03-13
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis , Derek Edward Williams
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis , Derek Edward Williams
IPC分类号： G06F9/46 , G06F12/00 , G06F13/36 , G06F13/42
CPC分类号： G06F9/52
摘要： A method of synchronizing an initiating processing unit in a multi-processor computer system with other processing units in the system, by assigning a unique tag for each processing unit, and issuing synchronization messages which include the unique tag of an initiating processing unit. The processing units each have a snoop queue for receiving snoop operations and corresponding tags associated with instructions issued by an initiating processing unit, and the processors examine their respective snoop queues to determine whether any snoop operation in those queues has a tag which is the unique tag of the initiating processing unit. A retry message is sent to the initiating processing unit from any of the other processing units which determine that a snoop operation in a snoop queue has a tag which is the unique tag of the initiating processing unit. In response to the retry message, the initiating processing unit re-issues the synchronization message, and the other processors re-examine their respective snoop queues, in response to the re-issuing of the synchronization message, to determine whether any snoop operation in those queues still has a tag which is the unique tag of the initiating processing unit.
摘要翻译：一种将多处理器计算机系统中的发起处理单元与系统中的其他处理单元同步的方法，通过为每个处理单元分配唯一标签，以及发出包括发起处理单元的唯一标签的同步消息。处理单元各自具有用于接收窥探操作的窥探队列和与由发起处理单元发出的指令相关联的对应标签，并且处理器检查它们各自的窥探队列以确定这些队列中的任何窥探操作是否具有作为唯一标签的标签的启动处理单元。重试消息从确定窥探队列中的窥探操作具有作为发起处理单元的唯一标签的标签的任何其他处理单元发送到发起处理单元。响应于重试消息，发起处理单元重新发布同步消息，并且其他处理器响应于重发同步消息而重新检查其相应的窥探队列，以确定是否有任何窥探操作队列仍然具有作为启动处理单元的唯一标签的标签。

86. 发明授权

US6026470A Software-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels 失效
标题翻译：软件管理的可编程组合缓存机制监控高速缓存未命中以选择性地实现多个关联级别
公开(公告)号：US6026470A
公开(公告)日：2000-02-15
申请号：US839546
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0864
摘要： A method of providing programmable associativity in a cache used by a processor of a computer system is disclosed. A congruence class of a memory block is defined using a first mapping function, providing a first associativity level of the cache. Program instructions in the processor select a second associativity level of a known appropriate level, and implement the second associativity level in the cache using a second mapping function. Application software may provide the program instructions, wherein the application software has procedures that may result in cache "strides" at particular associativity levels, and the known appropriate level is chosen to lessen memory latencies due to strides. Alternatively, the program instructions may be part of an operating system which monitors memory address requests, determines how efficient a procedure will operate at different associativity levels, and selects a most efficient level for the known appropriate level. The program instructions may select the associativity level by setting a value in a bit facility corresponding to the desired mapping function.
摘要翻译：公开了一种在由计算机系统的处理器使用的高速缓存中提供可编程关联性的方法。使用第一映射函数来定义存储器块的同余类，从而提供高速缓存的第一组合级别。处理器中的程序指令选择已知适当级别的第二关联级别，并且使用第二映射函数来实现高速缓存中的第二关联级别。应用软件可以提供程序指令，其中应用软件具有可能导致高速缓存在特定关联性级别“大步”的过程，并且选择已知的适当级别以减少由于步幅引起的存储器延迟。或者，程序指令可以是监视存储器地址请求的操作系统的一部分，确定程序在不同的关联级别下的操作有效性，并为已知的适当级别选择最有效的级别。程序指令可以通过设置与期望映射函数相对应的位设施中的值来选择关联性级别。

87. 发明授权

US5978888A Hardware-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels 失效
标题翻译：硬件管理的可编程组合缓存机制监控高速缓存未命中，以选择性地实现多个组合级别
公开(公告)号：US5978888A
公开(公告)日：1999-11-02
申请号：US839550
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F12/08
CPC分类号： G06F12/0864
摘要： A method of providing programmable associativity in a cache used by a processor of a computer system is disclosed. A congruence class of a memory block is defined using a first mapping function, providing a first associativity level of the cache. A logic unit connected to the cache monitors cache misses as the cache uses the first associativity level, and selects other associativity levels based on the cache misses, using other mapping functions. The logic unit has incorporated therein means for selecting the other associativity levels based on a rate of the cache misses in a particular congruence class. The congruence class may be defined by associating the memory block with a particular set of cache blocks in the cache, based on a first portion of an address of the memory block, and the other mapping functions may be implemented by dividing the particular set into subsets and selecting a subset for the memory block based on a second portion of the address.
摘要翻译：公开了一种在由计算机系统的处理器使用的高速缓存中提供可编程关联性的方法。使用第一映射函数来定义存储器块的同余类，从而提供高速缓存的第一组合级别。连接到高速缓存的逻辑单元监视高速缓存未命中，因为高速缓存使用第一关联性级别，并且使用其他映射功能，基于高速缓存未命中选择其他关联性级别。逻辑单元已经结合有用于基于特定同余类中的高速缓存未命中的速率来选择其他关联性级别的装置。可以通过基于存储器块的地址的第一部分将存储器块与高速缓存中的特定的一组高速缓存块相关联来定义同余类，并且可以通过将特定集合划分为子集来实现其他映射函数以及基于所述地址的第二部分来选择所述存储器块的子集。

88. 发明授权

US5978871A Method of layering cache and architectural specific functions for operation splitting 失效
标题翻译：分层缓存和架构特定功能的方法
公开(公告)号：US5978871A
公开(公告)日：1999-11-02
申请号：US834114
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis , Derek Edward Williams
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis , Derek Edward Williams
IPC分类号： G06F12/08 , G06F13/16 , G06F13/00 , G06F17/10
CPC分类号： G06F12/0893 , G06F13/1668
摘要： Cache and architectural specific functions within a cache controller are layered to permit complex operations to be split into equivalent simple operations. Architectural variants of basic operations may thus be devolved into distinct cache and architectural operations and handled separately. The logic supporting the complex operations may thus be simplified and run faster.
摘要翻译：高速缓存控制器中的缓存和架构特定功能被分层，以允许将复杂操作分成等效的简单操作。因此，基础操作的架构变体可以被分配到不同的缓存和架构操作中并分开处理。因此，支持复杂操作的逻辑可以被简化并且运行得更快。

89. 发明授权

US5974507A Optimizing a cache eviction mechanism by selectively introducing different levels of randomness into a replacement algorithm 失效
标题翻译：通过选择性地将不同级别的随机性引入替换算法来优化缓存驱逐机制
公开(公告)号：US5974507A
公开(公告)日：1999-10-26
申请号：US837512
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F12/08 , G06F12/12 , G06F12/02
CPC分类号： G06F12/127 , G06F12/123 , G06F12/0848 , G06F12/0864
摘要： A method of improving operation of a cache used by a processor of a computer system by introducing a level of randomness into a replacement algorithm used by the cache in order to lessen "strides" within the cache is disclosed. Different levels of randomness may be introduced into the replacement algorithm at different times to optimize the cache for different procedures running on the processor. The level of randomness can be selectively introduced by using a basic replacement algorithm to select a subset of a congruence class, and one or more random bits are then used to select a specific cache block within the subset for eviction. The basic replacement algorithm can be a least recently used algorithm. There may be three levels of randomness for a 4-way set associative cache, and there may be four levels of randomness for an 8-way set associative cache.
摘要翻译：公开了一种改进由计算机系统的处理器使用的缓存的操作的方法，其通过将高级别的随机性引入由高速缓存使用的替换算法中以减轻高速缓存内的“跨步”。可以在不同时间将不同级别的随机性引入到替换算法中，以针对在处理器上运行的不同过程优化高速缓存。可以通过使用基本替换算法选择一致等级的子集来选择性地引入随机性的水平，然后使用一个或多个随机比特来选择该子集内的特定高速缓存块进行驱逐。基本替换算法可以是最近最少使用的算法。对于4路组关联缓存，可能存在三个随机性级别，并且对于8路组关联高速缓存可能存在四个级别的随机性。

90. 发明授权

US5940856A Cache intervention from only one of many cache lines sharing an unmodified value 失效
标题翻译：缓存干预只能从许多缓存行之一共享一个未修改的值
公开(公告)号：US5940856A
公开(公告)日：1999-08-17
申请号：US837516
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , John Steven Dodson , John Michael Kaiser , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , John Michael Kaiser , Jerry Don Lewis
IPC分类号： G06F15/16 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0831
摘要： A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into at least two caches, the caches are marked as containing shared, unmodified copies of the value and, when a requesting processing unit issues a message indicating that it desires to read the value, a given one of the caches transmits a response indicating that the given cache can source the value. The response is transmitted in response to the cache snooping the message from an interconnect which is connected to the requesting processing unit. The response is detected by system logic and forwarded from the system logic to the requesting processing unit. The cache then sources the value to an interconnect which is connected to the requesting processing unit. The system memory detects the message and would normally source the value, but the response informs the memory device that the value is to be sourced by the cache instead. Since the cache latency can be much less than the memory latency, the read performance can be substantially improved with this new protocol.
摘要翻译：公开了一种改善与多处理器计算机系统中的读取类型操作相关联的存储器延迟的方法。在将值（数据或指令）从系统存储器加载到至少两个高速缓存中之后，高速缓存被标记为包含值的未修改的共享副本，并且当请求处理单元发出指示期望读取值的消息时，给定的一个高速缓存发送指示给定高速缓存可以输出该值的响应。该响应响应于来自连接到请求处理单元的互连的高速缓存窥探消息而被发送。响应由系统逻辑检测并从系统逻辑转发到请求处理单元。高速缓存然后将该值输出到连接到请求处理单元的互连。系统内存检测到该消息，并且通常会发送该值，但响应通知存储设备该值将由缓存提供。由于缓存延迟可能远小于内存延迟，因此可以通过此新协议大大提高读取性能。

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