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81. 发明申请

US20050233514A1 PMD liner nitride films and fabrication methods for improved NMOS performance 有权
标题翻译： PMD衬垫氮化物膜和用于改善NMOS性能的制造方法
公开(公告)号：US20050233514A1
公开(公告)日：2005-10-20
申请号：US10827692
申请日：2004-04-19
申请人： Haowen Bu , Rajesh Khamankar , Douglas Grider
发明人： Haowen Bu , Rajesh Khamankar , Douglas Grider
IPC分类号： H01L21/336 , H01L21/4763 , H01L21/768 , H01L21/8238
CPC分类号： H01L29/7843 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L21/823807 , H01L29/665 , Y10S438/938
摘要： Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in all or a portion of the NMOS transistor to improve carrier mobility. The nitride layer (130) is initially deposited over the transistors at low temperature with high hydrogen content to provide a moderate tensile stress in the semiconductor body prior to back-end processing. Subsequent back-end thermal processing reduces the film hydrogen content and causes an increase in the applied tensile stress.
摘要翻译：提供半导体器件（102）和制造方法（10），其中在NMOS晶体管上形成氮化物膜（130）以在NMOS晶体管的全部或一部分中施加拉伸应力以改善载流子迁移率。氮化物层（130）最初以高氢含量在低温下沉积在晶体管上，以在后端处理之前在半导体本体中提供适度的拉伸应力。随后的后端热处理降低了膜的氢含量并且引起所施加的拉伸应力的增加。

82. 发明申请

US20050221564A1 System and method for mitigating oxide growth in a gate dielectric 审中-公开
公开(公告)号：US20050221564A1
公开(公告)日：2005-10-06
申请号：US11145674
申请日：2005-06-06
申请人： Malcolm Bevan , Haowen Bu , Hiroaki Niimi , Husam Alshareef
发明人： Malcolm Bevan , Haowen Bu , Hiroaki Niimi , Husam Alshareef
IPC分类号： H01L21/28 , H01L29/49 , H01L29/51 , H01L29/78 , H01L21/336
CPC分类号： H01L21/28202 , H01L29/4908 , H01L29/517 , H01L29/518 , H01L29/78
摘要： Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

83. 发明申请

US20050189660A1 Source drain and extension dopant concentration 审中-公开
标题翻译：源极漏极和延伸掺杂剂浓度
公开(公告)号：US20050189660A1
公开(公告)日：2005-09-01
申请号：US10858644
申请日：2004-06-02
申请人： Haowen Bu , Amitabh Jain , Wayne Bather , Stephanie Butler
发明人： Haowen Bu , Amitabh Jain , Wayne Bather , Stephanie Butler
IPC分类号： H01L21/336 , H01L29/78 , H01L29/76 , H01L21/338
CPC分类号： H01L29/6659 , H01L29/6656 , H01L29/7833
摘要： A method of forming a semiconductor device includes forming one or more sidewall spacer layers on the outer surface of a gate stack. At least one region of an at least partially formed semiconductor device is doped. First and second sidewall bodies are formed on opposing sides of the gate stack. The formation of the first and second sidewall bodies includes forming a first sidewall-forming layer on the outward surface of the gate stack and the sidewall spacer layers, exposing the semiconductor device to a heating cycle in a single wafer reactor, and forming a second sidewall-forming layer on the outward surface of the first sidewall-forming layer. The formation of the second sidewall-forming layer occurs in an environment that substantially minimizes dopant loss and deactivation in the at least one region of the partially formed semiconductor device.
摘要翻译：形成半导体器件的方法包括在栅叠层的外表面上形成一个或多个侧壁间隔层。至少部分形成的半导体器件的至少一个区域被掺杂。第一和第二侧壁体形成在栅极堆叠的相对侧上。第一和第二侧壁体的形成包括在栅极堆叠的外表面和侧壁间隔层上形成第一侧壁形成层，将半导体器件暴露于单个晶片反应器中的加热循环，以及形成第二侧壁在第一侧壁形成层的外表面上形成层。第二侧壁形成层的形成发生在基本上最小化部分形成的半导体器件的至少一个区域中的掺杂剂损失和失活的环境中。

84. 发明授权

US06927137B2 Forming a retrograde well in a transistor to enhance performance of the transistor 有权
标题翻译：在晶体管中形成逆行阱以增强晶体管的性能
公开(公告)号：US06927137B2
公开(公告)日：2005-08-09
申请号：US10725977
申请日：2003-12-01
申请人： Srinivasan Chakravarthi , Pr Chidambaram , Robert C. Bowen , Haowen Bu
发明人： Srinivasan Chakravarthi , Pr Chidambaram , Robert C. Bowen , Haowen Bu
IPC分类号： H01L21/265 , H01L21/336 , H01L21/425 , H01L29/10 , H01L29/78
CPC分类号： H01L29/6653 , H01L21/26586 , H01L29/1083 , H01L29/6659 , H01L29/7833 , Y10S438/91
摘要： A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.
摘要翻译：提供了在晶体管中形成逆行阱的方法。形成在基板和栅极之间具有基板，栅极和栅极氧化物层的晶体管结构。衬底包括通常位于栅极下方的沟道区域。将第一掺杂剂注入沟道区。将第二掺杂剂注入到衬底中以形成掺杂源极区和掺杂漏极区。将第三掺杂剂注入到栅极氧化物层中。进行源极/漏极退火以分别在掺杂源极区域和掺杂漏极区域中形成源极和漏极。源极/漏极退火使得沟道区域中的第一掺杂剂的一部分被第三掺杂剂吸引到栅极氧化物层中。

85. 发明申请

US20050118792A1 Forming a retrograde well in a transistor to enhance performance of the transistor 有权
公开(公告)号：US20050118792A1
公开(公告)日：2005-06-02
申请号：US10725977
申请日：2003-12-01
申请人： Srinivasan Chakravarthi , Pr Chidambaram , Robert Bowen , Haowen Bu
发明人： Srinivasan Chakravarthi , Pr Chidambaram , Robert Bowen , Haowen Bu
IPC分类号： H01L21/265 , H01L21/336 , H01L21/425 , H01L29/10 , H01L29/78
CPC分类号： H01L29/6653 , H01L21/26586 , H01L29/1083 , H01L29/6659 , H01L29/7833 , Y10S438/91
摘要： A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.

86. 发明申请

US20050110114A1 Capacitor formed on a recrystallized polysilicon layer and a method of manufacture therefor 审中-公开
标题翻译：在再结晶的多晶硅层上形成的电容器及其制造方法
公开(公告)号：US20050110114A1
公开(公告)日：2005-05-26
申请号：US10722013
申请日：2003-11-25
申请人： Jiong-Ping Lu , Haowen Bu , Clint Montgomery
发明人： Jiong-Ping Lu , Haowen Bu , Clint Montgomery
IPC分类号： H01L21/02 , H01L21/8242 , H01L29/00
CPC分类号： H01L28/40 , H01L27/1085
摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, among other elements, includes a recrystallized polysilicon layer 148 located over a gate electrode layer 143, a capacitor 170 located on the recrystallized polysilicon layer 148. The capacitor 170, in this embodiment, includes a first electrode 173, an insulator 175 located over the first electrode 173, and a second electrode 178 located over the insulator 175.
摘要翻译：本发明提供一种半导体器件及其制造方法以及包括半导体器件的集成电路。除了其他元件之外，半导体器件包括位于栅电极层143上的再结晶多晶硅层148，位于再结晶多晶硅层148上的电容器170。在该实施例中，电容器170包括第一电极173，位于第一电极173上方的绝缘体175和位于绝缘体175上方的第二电极178。

87. 发明申请

US20050059228A1 Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance 有权
公开(公告)号：US20050059228A1
公开(公告)日：2005-03-17
申请号：US10662850
申请日：2003-09-15
申请人： Haowen Bu , Shashank Ekbote , Rajesh Khamankar , Shaoping Tang , Freidoon Mehrad
发明人： Haowen Bu , Shashank Ekbote , Rajesh Khamankar , Shaoping Tang , Freidoon Mehrad
IPC分类号： H01L21/00 , H01L21/3205 , H01L21/336 , H01L21/44 , H01L21/4763 , H01L21/8238 , H01L21/84 , H01L29/08 , H01L29/76 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7845 , Y10S438/902
摘要： The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite-cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.

88. 发明授权

US06812073B2 Source drain and extension dopant concentration 有权
标题翻译：源极漏极和延伸掺杂剂浓度
公开(公告)号：US06812073B2
公开(公告)日：2004-11-02
申请号：US10316468
申请日：2002-12-10
申请人： Haowen Bu , Amitabh Jain , Wayne A. Bather , Stephanie Watts Butler
发明人： Haowen Bu , Amitabh Jain , Wayne A. Bather , Stephanie Watts Butler
IPC分类号： H01L2100
CPC分类号： H01L29/6659 , H01L29/6656 , H01L29/7833
摘要： A method of forming a semiconductor device includes forming one or more sidewall spacer layers on the outer surface of a gate stack. At least one region of an at least partially formed semiconductor device is doped. First and second sidewall bodies are formed on opposing sides of the gate stack. The formation of the first and second sidewall bodies includes forming a first sidewall-forming layer on the outward surface of the gate stack and the sidewall spacer layers, exposing the semiconductor device to a heating cycle in a single wafer reactor, and forming a second sidewall-forming layer on the outward surface of the first sidewall-forming layer. The formation of the second sidewall-forming layer occurs in an environment that substantially minimizes dopant loss and deactivation in the at least one region of the partially formed semiconductor device.
摘要翻译：形成半导体器件的方法包括在栅叠层的外表面上形成一个或多个侧壁间隔层。至少部分形成的半导体器件的至少一个区域被掺杂。第一和第二侧壁体形成在栅极堆叠的相对侧上。第一和第二侧壁体的形成包括在栅极堆叠的外表面和侧壁间隔层上形成第一侧壁形成层，将半导体器件暴露于单个晶片反应器中的加热循环，以及形成第二侧壁在第一侧壁形成层的外表面上形成层。第二侧壁形成层的形成发生在基本上最小化部分形成的半导体器件的至少一个区域中的掺杂剂损失和失活的环境中。

89. 发明授权

US08101476B2 Stress memorization dielectric optimized for NMOS and PMOS 有权
标题翻译：针对NMOS和PMOS优化的应力记忆电介质
公开(公告)号：US08101476B2
公开(公告)日：2012-01-24
申请号：US12541335
申请日：2009-08-14
申请人： Kanan Garg , Haowen Bu , Mahalingam Nandakumar , Song Zhao
发明人： Kanan Garg , Haowen Bu , Mahalingam Nandakumar , Song Zhao
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/3185 , H01L21/823807 , H01L29/7843 , H01L29/7845
摘要： A method for forming a tensile SiN stress layer for stress memorization enhancement of NMOS transistors with a high Si—H/N—H bond ratio that does not degrade PMOS transistors. A CMOS integrated circuit is processed through a NMOS source and drain implant but not through NMOS source and drain anneal. A SiN dielectric layer is deposited such that an area ratio of a Si—H peak to a N—H peak in a FTIR spectrum is greater than 7 and a tensile stress of the SiN dielectric is greater than 150 MPa. The CMOS integrated circuit is annealed after deposition of the SiN dielectric layer and the SiN dielectric layer is removed from at least a part of the integrated circuit.
摘要翻译：一种用于形成具有不降低PMOS晶体管的高Si-H / N-H键比的NMOS晶体管的应力记忆增强的拉伸SiN应力层的方法。 CMOS集成电路通过NMOS源极和漏极注入而不是通过NMOS源极和漏极退火进行处理。沉积SiN电介质层，使得FTIR光谱中Si-H峰与N-H峰的面积比大于7，并且SiN电介质的拉伸应力大于150MPa。在沉积SiN电介质层之后对CMOS集成电路进行退火，并且从集成电路的至少一部分去除SiN介电层。

90. 发明授权

US08084787B2 PMD liner nitride films and fabrication methods for improved NMOS performance 有权
标题翻译： PMD衬垫氮化物膜和用于改善NMOS性能的制造方法
公开(公告)号：US08084787B2
公开(公告)日：2011-12-27
申请号：US11740426
申请日：2007-04-26
申请人： Haowen Bu , Rajesh Khamankar , Douglas T. Grider
发明人： Haowen Bu , Rajesh Khamankar , Douglas T. Grider
IPC分类号： H01L27/118
CPC分类号： H01L29/7843 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L21/823807 , H01L29/665 , Y10S438/938
摘要： Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in ail or a portion of the NMOS transistor to improve carrier mobility. The nitride layer (130) is initially deposited over the transistors at low temperature with high hydrogen content to provide a moderate tensile stress in the semiconductor body prior to back-end processing. Subsequent back-end thermal processing reduces the film hydrogen content and causes an increase in the applied tensile stress.
摘要翻译：提供半导体器件（102）和制造方法（10），其中在NMOS晶体管上形成氮化物膜（130），以在NMOS晶体管的一部分或一部分中施加拉伸应力以改善载流子迁移率。氮化物层（130）最初以高氢含量在低温下沉积在晶体管上，以在后端处理之前在半导体本体中提供适度的拉伸应力。随后的后端热处理降低了膜的氢含量并且引起所施加的拉伸应力的增加。

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