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81. 发明申请

US20070162156A1 Low powered activation electronic device 有权
标题翻译：低功率激活电子设备
公开(公告)号：US20070162156A1
公开(公告)日：2007-07-12
申请号：US11724960
申请日：2007-03-16
申请人： Jack Chu
发明人： Jack Chu
IPC分类号： G05B11/01
CPC分类号： H03K17/9645 , A61F13/42 , A63H3/36 , H01H2239/074
摘要： A low powered activation electronic device includes a power source, an electronic circuit, having two spaced apart electrodes, electrically connected to the power source to form an opened circuit, and two fabric contacts made of textile material provided at the two electrodes of the electronic circuit, wherein the electronic circuit is formed a closed circuit to activate the electronic device in responsive to a physical touch by a human operator at the two fabric contacts.
摘要翻译：低功率激活电子设备包括电源，电子电路，具有两个间隔开的电极，电连接到电源以形成开路，以及由设置在电子电路的两个电极处的纺织材料制成的两个织物触点，其中所述电子电路形成闭合电路，以响应于所述两个织物触点处的操作者的物理触摸来激活所述电子设备。

82. 发明申请

US20070148939A1 Low leakage heterojunction vertical transistors and high performance devices thereof 审中-公开
标题翻译：低漏极异质结垂直晶体管及其高性能器件
公开(公告)号：US20070148939A1
公开(公告)日：2007-06-28
申请号：US11317285
申请日：2005-12-22
申请人： Jack Chu , Qiqing Ouyang
发明人： Jack Chu , Qiqing Ouyang
IPC分类号： H01L21/3205
CPC分类号： H01L21/823885 , H01L21/823807 , H01L29/045 , H01L29/161 , H01L29/165 , H01L29/778 , H01L29/7781 , H01L29/7782 , H01L29/7789 , H01L29/7828 , H01L29/7848 , H01L29/78642
摘要： A method for forming and the structure of a vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry are described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (i.e., B and P) into the body. The invention reduces the problem of short channel effects such as drain induced barrier lowering and the leakage current from the source to drain regions via the hetero-junction and while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials. The problem of scalability of the gate length below 100 nm is overcome by the heterojunction between the source and body regions.
摘要翻译：描述了一种用于形成场效应晶体管，场效应晶体管和CMOS电路的垂直沟道结构的方法，其在垂直单晶半导体结构的侧壁上结合有漏极，主体和源极区域，其中异质结为形成在晶体管的源极和主体之间，其中源极区域和沟道独立地相对于体区域进行晶格应变，并且其中漏极区域包含碳掺杂区域以防止掺杂剂（即，B和P）扩散到身体。本发明减少了短沟道效应的问题，例如漏极引起的栅极降低和从源极到漏极区域的漏电流经由异质结，并且同时独立地允许沟道区域中的晶格应变，以通过选择半导体材料增加迁移率。栅极长度低于100nm的可扩展性的问题通过源极和体区之间的异质结来克服。

83. 发明申请

US20070055346A1 Method and apparatus for delivery of a treatment element in a blood vessel 审中-公开
标题翻译：用于在血管中递送治疗元件的方法和装置
公开(公告)号：US20070055346A1
公开(公告)日：2007-03-08
申请号：US11219437
申请日：2005-09-02
申请人： Jack Chu , Brian Raze
发明人： Jack Chu , Brian Raze
IPC分类号： A61F2/06
CPC分类号： A61F2/07 , A61F2/90 , A61F2002/067 , A61F2002/075 , A61F2002/077 , A61F2002/8483
摘要： An excluding device is inserted in a vessel. An excluded space is formed between a portion of a wall of the vessel and a portion of an exterior surface of the excluding device. A treatment element is passed through a channel of the excluding device into the excluded space. The channel is sealed using a cuff or patch after the passing of the treatment element(s) such as fill material or drugs and drug releasing elements.
摘要翻译：排除装置插入船只。在容器的壁的一部分和排除装置的外表面的一部分之间形成排除空间。治疗元件通过排除装置的通道进入排除空间。在通过处理元件（例如填充材料或药物和药物释放元件）之后，使用袖带或贴片密封通道。

84. 发明申请

US20060194422A1 Abrupt "delta-like" doping in Si and SiGe films by UHV-CVD 有权
标题翻译：通过UHV-CVD在Si和SiGe薄膜中进行突变“三角形”掺杂
公开(公告)号：US20060194422A1
公开(公告)日：2006-08-31
申请号：US11414091
申请日：2006-04-28
申请人： Frank Cardone , Jack Chu , Khalid Ismail
发明人： Frank Cardone , Jack Chu , Khalid Ismail
IPC分类号： H01L21/22 , H01L21/38
CPC分类号： H01L29/36 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/26506 , H01L29/1054 , H01L29/41783 , H01L29/66431 , H01L29/66477 , H01L29/665 , H01L29/66575 , H01L29/6659 , H01L29/66628 , H01L29/7833
摘要： A structure and method of forming an abrupt doping profile is described incorporating a substrate, a first epitaxial layer of Ge less than the critical thickness having a P or As concentration greater than 5×1019 atoms/cc, and a second epitaxial layer having a change in concentration in its first 40 OE from the first layer of greater than 1×1019 P atoms/cc. Alternatively, a layer of SiGe having a Ge content greater than 0.5 may be selectively amorphized and recrystalized with respect to other layers in a layered structure. The invention overcomes the problem of forming abrupt phosphorus profiles in Si and SiGe layers or films in semiconductor structures such as CMOS, MODFET's, and HBT's.
摘要翻译：描述了形成突变掺杂分布的结构和方法，其结合基板，Ge的第一外延层Ge小于具有大于5×10 19原子/ cc的P或As浓度的临界厚度，以及第二外延层在其第一层40 OE中的浓度随着大于1×10 19原子/ cc的第一层而变化。或者，具有Ge含量大于0.5的SiGe层可以相对于分层结构中的其它层选择性地非晶化并重结晶。本发明克服了在诸如CMOS，MODFET和HBT等半导体结构中的Si和SiGe层或膜中形成突变磷分布的问题。

85. 发明申请

US20060136050A1 Autologous Growth Factors to Promote Tissue In-Growth in Vascular Device 审中-公开
标题翻译：自体生长因子促进组织生长在血管装置中
公开(公告)号：US20060136050A1
公开(公告)日：2006-06-22
申请号：US11276518
申请日：2006-03-03
申请人： Jack Chu , Scott Doig , Brian Fernandes , Trevor Huang , Josiah Wilcox
发明人： Jack Chu , Scott Doig , Brian Fernandes , Trevor Huang , Josiah Wilcox
IPC分类号： A61F2/06
CPC分类号： A61L27/3616 , A61L27/3641 , A61L27/3645 , A61L27/54 , A61L2300/414
摘要： Methods and devices for ameliorating stent graft migration and endoleak using treatment site-specific cell growth promoting compositions in combination with stent grafts are disclosed. Also disclosed is coating of autologous growth factor compositions onto stent grafts prior to stent graft implantation. Additional embodiments include stent grafts having autologous growth factor composition coatings useful for treating aneurysms.
摘要翻译：公开了使用处理位点特异性细胞生长促进组合物与支架移植物组合来改善支架移植物迁移和内漏的方法和装置。还公开了在支架移植物植入之前将自体生长因子组合物涂覆到覆膜支架上。另外的实施方案包括具有用于治疗动脉瘤的自体生长因子组合物涂层的支架移植物。

86. 发明申请

US20060135942A1 Methods and Devices to Deliver Injected Agents to an Aneurysm Site 有权
标题翻译：将注射剂递送到动脉瘤部位的方法和装置
公开(公告)号：US20060135942A1
公开(公告)日：2006-06-22
申请号：US11276517
申请日：2006-03-03
申请人： Brian Fernandes , Jack Chu
发明人： Brian Fernandes , Jack Chu
IPC分类号： A61M31/00
CPC分类号： A61L27/3616 , A61L27/3641 , A61L27/3645 , A61L27/54 , A61L2300/414
摘要： Method and devices to administer a bioactive material within a vessel while maintaining nearly-constant pressure within the vessel are disclosed. In one embodiment the methods and devices include a multi-lumen catheter to administer bioactive materials and simultaneously drain or evacuate excess fluid or bio-inactive materials at an aneurysm site within a vessel.
摘要翻译：公开了在容器内施用生物活性物质同时保持容器内几乎恒定的压力的方法和装置。在一个实施方案中，所述方法和装置包括多腔导管，用于施用生物活性材料并同时在容器内的动脉瘤部位排出或排出多余的流体或生物惰性材料。

87. 发明申请

US20060054891A1 Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques 有权
标题翻译：使用晶片接合技术产生无缺陷的高Ge含量（> 25％）绝缘体上硅（SGOI）衬底的方法
公开(公告)号：US20060054891A1
公开(公告)日：2006-03-16
申请号：US10939736
申请日：2004-09-13
申请人： Jack Chu , Michael Cobb , Philip Saunders , Leathen Shi
发明人： Jack Chu , Michael Cobb , Philip Saunders , Leathen Shi
IPC分类号： H01L29/12 , H01L21/18
CPC分类号： H01L21/76254 , H01L21/0245 , H01L21/0251 , H01L29/1054
摘要： A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same.
摘要翻译：描述了使用低温晶片接合技术来实现包括具有大于约25原子％的高Ge含量的SiGe层的基本上无缺陷的SGOI衬底的方法。本申请中描述的晶片接合方法包括初始预结合退火步骤，其能够形成包含SiGe层和低温氧化物层之间的Si，Ge和O元素即界面SiGeO层的键合界面。本发明还提供了包含其的SGOI衬底和结构。

88. 发明申请

US20060030921A1 Intravascular securement device 审中-公开
标题翻译：血管内固定装置
公开(公告)号：US20060030921A1
公开(公告)日：2006-02-09
申请号：US10911042
申请日：2004-08-03
申请人： Jack Chu
发明人： Jack Chu
IPC分类号： A61F2/06
CPC分类号： A61F2/07 , A61F2/064 , A61F2/90 , A61F2002/065 , A61F2002/075 , A61F2220/0016 , A61F2230/005
摘要： A method and apparatus for a securement device useful for the treatment of aneurysms includes a hub and, in one aspect, a plurality of arms or spikes in a star pattern extendable therefrom and into engagement with a blood vessel wall. The securement device may be deployed to anchor a secondary device, such as an exclusion device for example a stent graft, in position in a flow lumen and thereby prevent the migration of the exclusion device in the flow lumen. The arms may be positioned to penetrate through the exclusion device and thence into the flow lumen wall to provide such securement.
摘要翻译：用于治疗动脉瘤的固定装置的方法和装置包括轮毂，并且在一个方面中，可以从其延伸并与血管壁接合的星形图案中的多个臂或钉。固定装置可以被展开以将次要装置（例如例如支架移植物的排除装置）锚定在流动腔中的适当位置，从而防止排除装置在流动腔中迁移。臂可以被定位成穿过排除装置，从而进入流动腔壁以提供这种固定。

89. 发明申请

US20050184354A1 Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector 有权
标题翻译：制造高速CMOS兼容的绝缘体上的光电探测器的结构和方法
公开(公告)号：US20050184354A1
公开(公告)日：2005-08-25
申请号：US10785894
申请日：2004-02-24
申请人： Jack Chu , Gabriel Dehlinger , Alfred Grill , Steven Koester , Qiging Ouyang , Jeremy Schaub
发明人： Jack Chu , Gabriel Dehlinger , Alfred Grill , Steven Koester , Qiging Ouyang , Jeremy Schaub
IPC分类号： H01L31/101 , H01L31/075
CPC分类号： H01L31/101
摘要： The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.
摘要翻译：本发明解决了与Si CMOS技术兼容的高速高效光电探测器的问题。该结构由薄的SOI衬底上的Ge吸收层组成，并且使用隔离区，交替的n型和p型接触以及低电阻表面电极。该器件通过利用掩埋绝缘层来隔离衬底中产生的载流子，通过利用Ge吸收层在宽谱上具有高量子效率，通过利用薄的吸收层和窄电极间隔的低电压操作以及兼容性来实现高带宽通过其平面结构和使用IV族吸收材料的CMOS器件。用于制造光电检测器的方法使用在薄SOI或外延氧化物上的Ge的直接生长，以及随后的热退火以实现高质量的吸收层。该方法限制可用于相互扩散的Si的量，从而允许Ge层退火，而不会导致Ge层被下面的Si大量稀释。

90. 发明申请

US20050145941A1 High performance strained silicon FinFETs device and method for forming same 有权
标题翻译：高性能应变硅FinFET器件及其形成方法
公开(公告)号：US20050145941A1
公开(公告)日：2005-07-07
申请号：US10751916
申请日：2004-01-07
申请人： Stephen Bedell , Kevin Chan , Dureseti Chidambarrao , Silke Christiansen , Jack Chu , Anthony Domenicucci , Kam-Leung Lee , Anda Mocuta , John Ott , Qiqing Ouyang
发明人： Stephen Bedell , Kevin Chan , Dureseti Chidambarrao , Silke Christiansen , Jack Chu , Anthony Domenicucci , Kam-Leung Lee , Anda Mocuta , John Ott , Qiqing Ouyang
IPC分类号： H01L21/336 , H01L21/84 , H01L27/01 , H01L27/12 , H01L29/786
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.
摘要翻译：应变的Fin场效应晶体管（FinFET）（及其形成方法）包括具有侧壁的松弛的第一材料和形成在第一材料的侧壁上的应变的第二材料。松弛的第一材料和应变的第二材料形成FinFET的鳍。

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