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81. 发明授权

US08145868B2 Method and system for providing frame start indication in a memory system having indeterminate read data latency 有权
标题翻译：在具有不确定的读数据延迟的存储器系统中提供帧起始指示的方法和系统
公开(公告)号：US08145868B2
公开(公告)日：2012-03-27
申请号：US11843150
申请日：2007-08-22
申请人： Paul W. Coteus , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
发明人： Paul W. Coteus , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F12/00
CPC分类号： G06F13/1657 , G06F13/1673
摘要： A method and system for providing frame start indication in a memory system having indeterminate read data latency. The method includes receiving a data transfer and determining if the data transfer includes a frame start indicator. The method also includes capturing the data transfer and “n” subsequent data transfers in response to determining that the data transfer includes a frame start indicator. The data transfer and the “n” subsequent data transfers comprise a data frame.
摘要翻译：一种用于在具有不确定的读数据延迟的存储器系统中提供帧起始指示的方法和系统。该方法包括接收数据传输并确定数据传输是否包括帧起始指示符。响应于确定数据传输包括帧起始指示符，该方法还包括捕获数据传输和“n”次后续数据传输。数据传输和“n”个后续数据传输包括数据帧。

82. 发明授权

US07984329B2 System and method for providing DRAM device-level repair via address remappings external to the device 有权
标题翻译：通过设备外部的地址重映射提供DRAM设备级修复的系统和方法
公开(公告)号：US07984329B2
公开(公告)日：2011-07-19
申请号：US11849452
申请日：2007-09-04
申请人： Luis A. Lastras-Montano , Darren L. Anand , Jeffrey H. Dreibelbis , Charles A. Kilmer , Warren E. Maule , Robert B. Tremaine
发明人： Luis A. Lastras-Montano , Darren L. Anand , Jeffrey H. Dreibelbis , Charles A. Kilmer , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F11/00
CPC分类号： G11C29/76 , G11C11/401
摘要： A system and method for providing DRAM device-level repair via address remappings external to the device. A system includes a memory controller having an interface to one or more memory devices via a memory module. The memory devices include addressable redundant and non-redundant memory blocks. The memory controller also includes a mechanism for utilizing one or more redundant memory blocks in place of one or more failing non-redundant memory blocks via an address remapping external to the memory device. The remapping occurs while the system is on-line.
摘要翻译：一种用于通过设备外部的地址重映射提供DRAM设备级修复的系统和方法。系统包括存储器控制器，其经由存储器模块具有到一个或多个存储器设备的接口。存储器件包括可寻址冗余和非冗余存储器块。存储器控制器还包括一种机构，用于经由存储器件外部的地址重新映射来代替一个或多个故障非冗余存储器块来利用一个或多个冗余存储器块。重新映射发生在系统在线时。

83. 发明申请

US20110126200A1 Scheduling for functional units on simultaneous multi-threaded processors 失效
标题翻译：在同时多线程处理器上调度功能单元
公开(公告)号：US20110126200A1
公开(公告)日：2011-05-26
申请号：US11488970
申请日：2006-07-19
申请人： Orran Y. Krieger , Bryan S. Rosenburg , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
发明人： Orran Y. Krieger , Bryan S. Rosenburg , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F9/46
CPC分类号： G06F9/5033
摘要： A method and system for scheduling threads on simultaneous multithreaded processors are disclosed. Hardware and operating system communicate with one another providing information relating to thread attributes for threads executing on processing elements. The operating system determines thread scheduling based on the information.
摘要翻译：公开了一种用于在同时多线程处理器上调度线程的方法和系统。硬件和操作系统彼此通信，提供与处理元件上执行的线程的线程属性相关的信息。操作系统根据信息确定线程调度。

84. 发明授权

US07685392B2 Providing indeterminate read data latency in a memory system 失效
标题翻译：在存储器系统中提供不确定的读取数据延迟
公开(公告)号：US07685392B2
公开(公告)日：2010-03-23
申请号：US11289193
申请日：2005-11-28
申请人： Paul W. Coteus , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
发明人： Paul W. Coteus , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F13/18 , G06F13/372 , G06F13/376
CPC分类号： G06F13/1657 , G06F13/1673
摘要： A method for providing indeterminate read data latency in a memory system. The method includes determining if a local data packet has been received and storing it into a buffer device. The method also includes determining if the buffer device contains a data packet and determining if an upstream driver for transmitting data packets to a memory controller via an upstream channel is idle, and in response thereto the data packet is transmitted to the upstream driver. The method further includes determining if an upstream data packet has been received and the upstream driver is not idle, then the upstream data packet is stored into the buffer device. The upstream data packet is selectively transmitted to the upstream driver. If the upstream driver is not idle, then any data packets in progress are continued being transmitted to the upstream driver.
摘要翻译：一种用于在存储器系统中提供不确定的读取数据延迟的方法。该方法包括确定本地数据分组是否已被接收并将其存储到缓冲设备中。该方法还包括确定缓冲器装置是否包含数据包，并确定是否经由上游信道将数据包发送到存储器控制器的上游驱动器是空闲的，并且响应于此数据包被发送到上游驱动器。该方法还包括确定是否已经接收到上游数据分组，并且上游驱动器不空闲，则上游数据分组被存储到缓冲设备中。上游数据包被选择性地发送到上游驱动器。如果上游驱动程序不空闲，那么正在进行的任何数据分组都将继续传输到上游驱动程序。

85. 发明授权

US07627732B2 Memory systems for automated computing machinery 失效
标题翻译：自动计算机的存储系统
公开(公告)号：US07627732B2
公开(公告)日：2009-12-01
申请号：US12102034
申请日：2008-04-14
申请人： Paul W. Coteus , Kevin C. Gower , Robert B. Tremaine
发明人： Paul W. Coteus , Kevin C. Gower , Robert B. Tremaine
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , H04L12/50 , H04Q11/00
CPC分类号： G06F13/1684 , Y02D10/14
摘要： Design structures embodied in machine readable medium are provided. Embodiments of the design structure include a memory system comprising: a memory controller; a memory bus terminator; a high speed memory bus that interconnects the memory controller, the memory bus terminator, and at least one memory module; and the at least one memory module, the memory module comprising at least one memory hub device, high speed random access memory served by the memory hub device, two bus signal ports, and a segment of the high speed memory bus fabricated on the memory module so as to interconnect the bus signal ports and the memory hub device, the high speed memory bus connected to the memory hub device by a negligible electrical stub.
摘要翻译：提供体现在机器可读介质中的设计结构。设计结构的实施例包括存储器系统，包括：存储器控制器; 一个内存总线终端; 连接存储器控制器，存储器总线终端器和至少一个存储器模块的高速存储器总线; 和所述至少一个存储器模块，所述存储器模块包括至少一个存储器集线器设备，由所述存储器集线器设备服务的高速随机存取存储器，两个总线信号端口以及在所述存储器模块上制造的所述高速存储器总线的段以便将总线信号端口和存储器集线器设备互连，高速存储器总线通过可忽略的电接头连接到存储器集线器设备。

86. 发明授权

US07539842B2 Computer memory system for selecting memory buses according to physical memory organization information stored in virtual address translation tables 失效
标题翻译：计算机存储器系统，用于根据存储在虚拟地址转换表中的物理存储器组织信息来选择存储器总线
公开(公告)号：US07539842B2
公开(公告)日：2009-05-26
申请号：US11464503
申请日：2006-08-15
申请人： Robert B. Tremaine
发明人： Robert B. Tremaine
IPC分类号： G06F12/10
CPC分类号： G06F12/0607 , G06F12/10 , G06F13/28
摘要： Systems and methods for program directed memory access patterns including a memory system with a memory, a memory controller and a virtual memory management system. The memory includes a plurality of memory devices organized into one or more physical groups accessible via associated busses for transferring data and control information. The memory controller receives and responds to memory access requests that contain application access information to control access pattern and data organization within the memory. Responding to memory access request includes accessing one or more memory devices. The virtual memory management system includes: a plurality of page table entries for mapping virtual memory addresses to real addresses in the memory; a hint state responsive to application access information for indicating how real memory for associated pages is to be physically organized within the memory; and a means for conveying the hint state to the memory controller.
摘要翻译：用于程序定向存储器访问模式的系统和方法，包括具有存储器的存储器系统，存储器控制器和虚拟存储器管理系统。存储器包括被组织成一个或多个物理组的多个存储器件，可通过相关联的总线访问以传送数据和控制信息。存储器控制器接收并响应包含应用访问信息的存储器访问请求，以控制存储器内的访问模式和数据组织。响应于存储器访问请求包括访问一个或多个存储器设备。虚拟存储器管理系统包括：多个页表条目，用于将虚拟存储器地址映射到存储器中的实际地址; 响应于应用程序访问信息的指示状态，用于指示相关联的页面的实际存储器如何被物理地组织在存储器内; 以及用于将提示状态传送到存储器控制器的装置。

87. 发明申请

US20080263278A1 CACHE RECONFIGURATION BASED ON RUN-TIME PERFORMANCE DATA OR SOFTWARE HINT 有权
标题翻译：基于运行时性能数据或软件提示的缓存重新配置
公开(公告)号：US20080263278A1
公开(公告)日：2008-10-23
申请号：US12130752
申请日：2008-05-30
申请人： Xiaowei Shen , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
发明人： Xiaowei Shen , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F2212/1028 , G06F2212/601 , Y02D10/13
摘要： A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.
摘要翻译：提供了一种重新配置高速缓冲存储器的方法。一个方面中的方法可以包括分析访问高速缓冲存储器的执行实体的一个或多个特征，并且基于所分析的一个或多个特征重新配置高速缓存。分析特性的示例可以包括但不限于执行实体使用的数据结构，执行实体的预期参考模式，执行实体的类型，执行实体的热和功耗。等等重新配置可以包括但不限于高速缓冲存储器的相关性，可用于存储数据的高速缓冲存储器的量，高速缓冲存储器的相干粒度，高速缓存存储器的行大小等。

88. 发明申请

US20080022283A1 Quality of service scheduling for simultaneous multi-threaded processors 审中-公开
标题翻译：同步多线程处理器的服务质量调度
公开(公告)号：US20080022283A1
公开(公告)日：2008-01-24
申请号：US11488977
申请日：2006-07-19
申请人： Orran Y. Krieger , Bryan S. Rosenburg , Robert B. Tremaine , Robert W. Wisniewski
发明人： Orran Y. Krieger , Bryan S. Rosenburg , Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F9/46
CPC分类号： G06F9/505 , G06F9/3851 , G06F2209/5018 , G06F2209/5019 , G06F2209/508
摘要： A method and system for providing quality of service guarantees for simultaneous multithreaded processors are disclosed. Hardware and operating system communicate with one another providing information relating to thread attributes for threads executing on processing elements. The operating system controls scheduling of the threads based at least partly on the information communicated and provides quality of service guarantees.
摘要翻译：公开了一种用于提供同时多线程处理器的服务质量保证的方法和系统。硬件和操作系统彼此通信，提供与处理元件上执行的线程的线程属性相关的信息。操作系统至少部分地基于传达的信息来控制线程的调度，并提供服务质量保证。

89. 发明申请

US20080022076A1 Operating system thread scheduling for optimal heat dissipation 失效
标题翻译：操作系统线程调度，实现最佳散热
公开(公告)号：US20080022076A1
公开(公告)日：2008-01-24
申请号：US11482270
申请日：2006-07-07
申请人： Orran Y. Krieger , Bryan S. Rosenburg , Robert B. Tremaine , Robert W. Wisniewski
发明人： Orran Y. Krieger , Bryan S. Rosenburg , Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F15/00
CPC分类号： G06F9/5033 , G06F1/206 , G06F9/5094 , G06F2209/5013 , G06F2209/5018 , G06F2209/508 , Y02D10/22
摘要： A method and system for thread scheduling for optimal heat dissipation are provided. Temperature sensors measure temperature throughout various parts of a processor chip. The temperatures detected are reported to an operating system or the like for scheduling threads. In one aspect, the observed temperature values are recorded on registers. An operating system or the like reads the registers and schedules threads based on the temperature values.
摘要翻译：提供了一种用于最佳散热的线程调度的方法和系统。温度传感器测量处理器芯片各个部分的温度。检测到的温度被报告给操作系统等用于调度线程。在一个方面，观察到的温度值记录在寄存器上。操作系统等读取寄存器并基于温度值调度线程。

90. 发明申请

US20080010408A1 Cache reconfiguration based on run-time performance data or software hint 失效
标题翻译：基于运行时性能数据或软件提示的缓存重新配置
公开(公告)号：US20080010408A1
公开(公告)日：2008-01-10
申请号：US11481020
申请日：2006-07-05
申请人： Xiaowei Shen , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
发明人： Xiaowei Shen , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F2212/1028 , G06F2212/601 , Y02D10/13
摘要： A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.
摘要翻译：提供了一种重新配置高速缓冲存储器的方法。一个方面中的方法可以包括分析访问高速缓冲存储器的执行实体的一个或多个特征，并且基于所分析的一个或多个特征重新配置高速缓存。分析特性的示例可以包括但不限于执行实体使用的数据结构，执行实体的预期参考模式，执行实体的类型，执行实体的热和功耗。等等重新配置可以包括但不限于高速缓冲存储器的相关性，可用于存储数据的高速缓冲存储器的量，高速缓冲存储器的相干粒度，高速缓存存储器的行大小等。

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