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    • 82. 发明授权
    • Inverter device attenuating in-phase harmonic components of an
oscillating output signal
    • 变频器衰减振荡输出信号的同相谐波分量
    • US5422765A
    • 1995-06-06
    • US776858
    • 1991-10-16
    • Eiji KobayashiAkira Egawa
    • Eiji KobayashiAkira Egawa
    • H02M1/12H02M7/5387H03H7/09
    • H03H7/09H02M1/12H02M7/5387
    • An inverter device receives a D.C. power source as an input and performs a switching operation at a single frequency in response to a preset driving signal (Vg1, Vg2, Vg3, Vg4) to produce an A.C. voltage. A transmission transformer (CH) having two coils which have the same inductance and are magnetically closely coupled with each other is provided and the two coils (CH1, CH2) are connected with the same polarities to respective ones of one set of lines for transmitting the A.C. voltage. The impedance of the transmission transformer (CH) is so small that it is negligible with respect to a normal A.C. voltage of a positive phase mode. A harmonic voltage is in an in-phase mode and the transmission transformer (CH) exhibits an extremely high impedance with respect to the harmonic voltage, and thus prevents the creation of a current path. As a result, the waveform distortion of a voltage applied between the drain and source of MOS transistors (FET1, FET2, FET3, FET4) is reduced and the peak value is reduced.
    • 逆变器装置接收直流电源作为输入,并响应于预设的驱动信号(Vg1,Vg2,Vg3,Vg4)以单个频率执行切换操作,以产生交流电压。 提供了具有相同电感并且彼此磁耦合的两个线圈的变速器(CH),并且两个线圈(CH1,CH2)以相同的极性连接到一组线路中的相应的一组线路,用于发送 交流电压。 传输变压器(CH)的阻抗如此之小,相对于正相模式的正常交流电压可以忽略不计。 谐波电压处于同相模式,并且变压器(CH)相对于谐波电压具有极高的阻抗,因此防止了电流路径的产生。 结果,施加在MOS晶体管(FET1,FET2,FET3,FET4)的漏极和源极之间的电压的波形失真减小,峰值减小。
    • 89. 发明授权
    • Disk array device, parity data generating circuit for RAID and Galois field multiplying circuit
    • 磁盘阵列设备,用于RAID和伽罗瓦域乘法电路的奇偶校验数据产生电路
    • US07437658B2
    • 2008-10-14
    • US10989439
    • 2004-11-17
    • Eiji Kobayashi
    • Eiji Kobayashi
    • G06F11/00
    • G06F11/1076G06F2211/1054G06F2211/1057G11B20/1833
    • In this parity data generating circuit, a Galois field multiplying calculation is realized by performing data conversion by index table information generated from a Galois field multiplying table so that data for RAID6 are generated. A table check circuit inspects nonconformity of the index table information in advance by using results in which the Galois field multiplying table is indexed from different directions constructed by the longitudinal direction and the transversal direction. Data and parity for making the multiplying calculation are decomposed into plural data and parities by using this table check circuit, and index table information different from each other are allocated to these data and parities. Thus, a longitudinal index table making circuit and a transversal index table making circuit themselves are checked.
    • 在该奇偶校验数据生成电路中,通过由伽罗瓦域乘法表生成的索引表信息进行数据变换,生成用于RAID6的数据,来实现伽罗瓦域乘法运算。 表检查电路通过使用伽罗瓦域乘法表从由纵向和横向构成的不同方向分度的结果,预先检查索引表信息的不一致性。 通过使用该表检查电路,进行乘法运算的数据和奇偶校验被分解为多个数据和奇偶校验,并且将彼此不同的索引表信息分配给这些数据和奇偶校验。 因此,检查纵向索引表制作电路和横向索引表制作电路本身。