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81. 发明授权

US06448591B1 Metallization line layout 有权
标题翻译：金属化线布局
公开(公告)号：US06448591B1
公开(公告)日：2002-09-10
申请号：US09388894
申请日：1999-09-02
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L2348
CPC分类号： H01L23/528 , H01L21/76819 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： The present invention relates to metallization line layouts that minimize focus offset sensitivity by a substantial elimination of thin isolated metallization line segments that are inadequately patterned during formation of a mask. The present invention also relates to a metallization line layout that staggers unavoidable exposures. Embodiments of these metallization line layouts include enhanced terminal ends of isolated metallization lines, filled inter-metallization line spaces, and additional “dummy” metal shapes in open areas. The present invention also relates to a method of forming a metallization layer such that a substantially deposited, planarized interlayer dieletric layer can be formed without etchback or chemical-mechanical polishing
摘要翻译：本发明涉及通过基本上消除在形成掩模期间不充分图案化的薄隔离金属化线段而使焦点偏移灵敏度最小化的金属化线路布局。本发明还涉及交错不可避免的曝光的金属化线布局。这些金属化线路布置的实施例包括隔离的金属化线的增强的终端，填充的金属间化线空间以及开放区域中的附加“虚拟”金属形状。本发明还涉及一种形成金属化层的方法，使得可以在没有回蚀或化学机械抛光的情况下形成基本上沉积的平坦化的层间缺陷层

82. 发明授权

US06416907B1 Method for designing photolithographic reticle layout, reticle, and photolithographic process 有权
标题翻译：光刻标线布局，光罩和光刻工艺的设计方法
公开(公告)号：US06416907B1
公开(公告)日：2002-07-09
申请号：US09559262
申请日：2000-04-27
申请人： Amy A. Winder , Werner Juengling
发明人： Amy A. Winder , Werner Juengling
IPC分类号： G03F900
CPC分类号： G03F7/70433 , G03F1/26
摘要： There are provided methods of creating a phase shift mask, comprising storing a file representing a binary mask layout as one or more cells, or as a hierarchy of a plurality of cells, at least some of which cells contain printable shapes; for each cell, determining if the cell contains a printable shape; if the cell has a printable shape, determining if the cell will print desired features in a wafer fabrication process and if so, leaving the cell alone; if the cell has a printable shape which will not print desired features in the wafer fabrication process, providing phase shift areas adjacent the printable shape so that it will print desired features; and using the cells to produce a phase shift mask. There are further provided embodiments of steps for generating such phase shift areas. In addition, there are provided photolithographic processes comprising directing exposure onto a resist through a mask formed using such methods. There are further provided systems comprising a computer readable storage medium containing program instructions for execution by a processor to design a mask; and a processor for executing the program instructions stored on the computer readable storage medium for performing such methods.
摘要翻译：提供了创建相移掩模的方法，包括将表示二进制掩模布局的文件存储为一个或多个单元，或者存储多个单元的层级，其中至少一些单元包含可打印形状; 确定每个单元格是否包含可打印形状; 如果单元具有可打印形状，则确定单元是否将在晶片制造过程中打印期望的特征，如果是，则单独留下单元; 如果单元具有在晶片制造过程中不能打印所需特征的可打印形状，则提供与可打印形状相邻的相移区域，使得其将打印期望的特征; 并使用这些单元来产生相移掩模。还提供了用于产生这种相移区域的步骤的实施例。此外，提供了光刻工艺，其包括通过使用这种方法形成的掩模将曝光引导到抗蚀剂上。还提供了包括计算机可读存储介质的系统，该计算机可读存储介质包含用于由处理器执行以设计掩模的程序指令; 以及处理器，用于执行存储在计算机可读存储介质上的用于执行这些方法的程序指令。

83. 发明授权

US06337261B1 Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry 失效
标题翻译：形成集成电路的半导体处理方法和形成动态随机存取存储器（DRAM）电路的半导体处理方法
公开(公告)号：US06337261B1
公开(公告)日：2002-01-08
申请号：US09689237
申请日：2000-10-11
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L2104
CPC分类号： H01L27/10873 , H01L21/266 , H01L21/31116 , H01L21/31144 , H01L27/10894 , H01L29/6653
摘要： Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material of the substrate is etched through the openings. In one implementation, openings are contemporaneously formed in a photo masking layer over substrate areas where impurities are to be provided, and other areas where etching is to take place. In separate steps, the substrate is doped with impurities, and material of the substrate is etched through the mask openings. In another implementation, two conductive lines are formed over a substrate and a masking layer is formed over the conductive lines. Openings are formed in the masking layer in the same step, with one of the openings being received over one conductive line, and another of the openings being received over the other conductive line. Impurities provided through an opening into the substrate proximate one conductive line, and material from over the other conductive line is removed through the other opening to at least partially form a contact opening over the other conductive line.
摘要翻译：描述了形成集成电路，特别是动态随机存取存储器（DRAM）电路的半导体处理方法。在一个实施例中，使用单个掩蔽步骤在衬底上形成掩模开口，并且提供两种杂质，并且通过开口蚀刻衬底的材料。在一个实施方案中，在要设置杂质的衬底区域上的光掩模层中以及要进行蚀刻的其它区域同时形成开口。在单独的步骤中，衬底掺杂有杂质，并且通过掩模开口蚀刻衬底的材料。在另一实施方式中，在衬底上形成两条导线，并且在导电线上形成掩模层。在相同步骤中的掩模层中形成开口，其中一个开口被接纳在一个导电线上，另一个开口被接收在另一个导线上。杂质通过靠近一根导电线路的衬底提供到衬底中，并且来自另一导电线的材料通过另一个开口去除，以至少部分地在另一个导电线上形成接触开口。

84. 发明授权

US06331461B1 Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry 失效
公开(公告)号：US06331461B1
公开(公告)日：2001-12-18
申请号：US09422825
申请日：1999-10-21
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L218242
CPC分类号： H01L27/1085 , H01L21/0331 , H01L27/0207 , H01L27/10808 , H01L28/40 , Y10S438/947
摘要： Semiconductor processing methods include forming a plurality of patterned device outlines over a semiconductor substrate, forming electrically insulative partitions or spacers on at least a portion of the patterned device outlines, and forming a plurality of substantially identically shaped devices relative to the patterned device outlines. Individual formed devices are spaced from at least one other of the devices by a distance no more than a width of one of the electrically insulative spacers. In such manner, device pitch is reduced by almost fifty percent. According to one aspect, elongated electrically conductive lines are formed. According to another aspect, capacitors are formed which, according to a preferred embodiment form part of a dynamic random access memory (DRAM) array.

85. 发明授权

US06316327B1 Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry 失效
标题翻译：在衬底上形成器件的半导体加工方法，在衬底上形成器件阵列，在衬底上形成导线，以及在衬底上形成电容器阵列，以及集成电路
公开(公告)号：US06316327B1
公开(公告)日：2001-11-13
申请号：US09399586
申请日：1999-09-20
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L2120
CPC分类号： H01L27/1085 , H01L21/0331 , H01L27/0207 , H01L27/10808 , H01L28/40 , Y10S438/947
摘要： Semiconductor processing methods include forming a plurality of patterned device outlines over a semiconductor substrate, forming electrically insulative partitions or spacers on at least a portion of the patterned device outlines, and forming a plurality of substantially identically shaped devices relative to the patterned device outlines. Individual formed devices are spaced from at least one other of the devices by a distance no more than a width of one of the electrically insulative spacers. In such manner, device pitch is reduced by almost fifty percent. According to one aspect, elongated electrically conductive lines are formed. According to another aspect, capacitors are formed which, according to a preferred embodiment form part of a dynamic random access memory (DRAM) array.
摘要翻译：半导体处理方法包括在半导体衬底上形成多个图案化器件轮廓，在图案化器件轮廓的至少一部分上形成电绝缘隔板或间隔件，以及相对于图案化器件轮廓形成多个基本相同形状的器件。单独的成形装置与装置中的至少另一个间隔开不超过一个电绝缘间隔件的宽度的距离。以这种方式，器件间距减少了近百分之五十。根据一个方面，形成细长的导电线。根据另一方面，形成电容器，其根据优选实施例形成动态随机存取存储器（DRAM）阵列的一部分。

86. 发明授权

US06207571B1 Self-aligned contact formation for semiconductor devices 有权
标题翻译：用于半导体器件的自对准接触形成
公开(公告)号：US06207571B1
公开(公告)日：2001-03-27
申请号：US09515804
申请日：2000-02-29
申请人： Werner Juengling , Kirk Prall , Trung T. Doan , Guy T. Blalock , David Dickerson , David S. Becker
发明人： Werner Juengling , Kirk Prall , Trung T. Doan , Guy T. Blalock , David Dickerson , David S. Becker
IPC分类号： H01L2100
CPC分类号： H01L27/10894 , H01L21/316 , H01L21/31625 , H01L21/76897
摘要： In accordance with the present invention, there is provided a method for fabricating a contact on an integrated circuit, such as a DRAM. The method includes the following steps. A gate stack is formed on the integrated circuit. A spacer is formed on sidewalls of the gate stack. An insulating film is formed on the integrated circuit. The insulating film is planarized. Finally, a gate contact opening is formed through the planarized insulating film. In one embodiment, the gate contact opening is formed by removing the insulator, spacer and insulating film by etching. In this embodiment, the insulator, spacer and insulating film are etched at substantially similar rates. As a result, the integrated circuit is tolerant of mask misalignments, and does not over-etch field oxide or create silicon nitride slivers. In another embodiment, the planarizing step is performed with chemical mechanical planarization to form a substantially flat topography on the surface of the integrated circuit. Thus, the present invention does not require lithography equipment with a relatively large field of depth. In yet a third embodiment, the method may comprise additional steps, including forming additional dielectric on the integrated circuit. Then, gate and bitline contact openings are formed through the additional dielectric. Finally, gate and bitline contacts are formed in self-alignment to the gate stacks. This embodiment may be implemented by forming the gate and bitline contact openings with an etch that removes the additional dielectric, but does not substantially remove the spacer. As a result, the bitline contact cannot be inadvertently connected to a gate stack that functions as a wordline. This connection might disable the integrated circuit.
摘要翻译：根据本发明，提供了一种用于在诸如DRAM的集成电路上制造接触的方法。该方法包括以下步骤。在集成电路上形成栅极堆叠。在栅叠层的侧壁上形成间隔物。在集成电路上形成绝缘膜。绝缘膜平坦化。最后，通过平坦化绝缘膜形成栅极接触开口。在一个实施例中，通过蚀刻去除绝缘体，间隔物和绝缘膜来形成栅极接触开口。在该实施例中，以基本相似的速率蚀刻绝缘体，间隔物和绝缘膜。因此，集成电路容忍掩模未对准，并且不会过度蚀刻场氧化物或产生氮化硅条。在另一个实施例中，平面化步骤通过化学机械平面化进行，以在集成电路的表面上形成基本平坦的形貌。因此，本发明不需要具有相当大的深度场的光刻设备。在第三个实施例中，该方法可以包括额外的步骤，包括在集成电路上形成附加电介质。然后，通过附加电介质形成栅极和位线接触开口。最后，栅极和位线触点形成为与栅极堆叠自对准。该实施例可以通过用蚀刻去除附加电介质但不基本上去除间隔物的栅极和位线接触开口来实现。因此，位线接触不能无意中连接到用作字线的栅极堆叠。此连接可能会禁用集成电路。

87. 发明授权

US06207564B1 Method of forming self-aligned isolated plugged contacts 有权
标题翻译：形成自对准隔离堵塞接点的方法
公开(公告)号：US06207564B1
公开(公告)日：2001-03-27
申请号：US09237482
申请日：1999-01-26
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L2144
CPC分类号： H01L27/10844 , H01L21/76202 , H01L21/76897 , H01L27/105 , H01L27/10805
摘要： A method for preparing an SRAM or DRAM structure on a substrate with an oppositely doped well therein, a field oxide region extending above and between the well and the substrate, first and second N-MOS transistors on the silicon substrate, and a P-MOS transistor on the silicon well. The source and drain regions of each of the P-MOS transistor and the first and second N-MOS transistors each have a polysilicon plug making contact therewith. Each polysilicon plug is isolated one from another by nitride spacers, has the same doping as the region with which it makes contact, and is self-aligned to the nitride spacers lining the passage of the polysilicon plugs to their respective contacts on either the silicon substrate or the silicon well. The self-aligned nature of the polysilicon plugs is due to the nitride spacers formed by etchant selectivities and photoresist masks.
摘要翻译：一种用于在其上具有相对掺杂阱的衬底上制备SRAM或DRAM结构的方法，在阱和衬底之间以及阱和衬底之间延伸的场氧化物区域，硅衬底上的第一和第二N-MOS晶体管以及P-MOS 硅晶体管上的硅。每个P-MOS晶体管和第一和第二N-MOS晶体管的源极和漏极区域都具有与其接触的多晶硅插塞。每个多晶硅插塞通过氮化物间隔物彼此隔离，具有与其接触的区域相同的掺杂，并且与衬底上的多晶硅插塞通过其上的硅衬底上的它们各自的触点的氮化物衬垫自对准或硅井。多晶硅插塞的自对准性质是由于蚀刻剂选择性和光致抗蚀剂掩模形成的氮化物间隔物。

88. 发明授权

US06130137A Method of forming a resistor and integrated circuitry having a resistor construction 有权
标题翻译：形成电阻器的方法和具有电阻器结构的集成电路
公开(公告)号：US06130137A
公开(公告)日：2000-10-10
申请号：US170792
申请日：1998-10-13
申请人： Kirk Prall , Pierre C. Fazan , Aftab Ahmad , Howard E. Rhodes , Werner Juengling , Pai-Hung Pan , Tyler Lowrey
发明人： Kirk Prall , Pierre C. Fazan , Aftab Ahmad , Howard E. Rhodes , Werner Juengling , Pai-Hung Pan , Tyler Lowrey
IPC分类号： H01L21/02 , H01L21/20
CPC分类号： H01L28/20
摘要： A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars. An integrated circuit incorporating a resistor construction includes, i) a layer of semiconductive material; ii) a pair of electrically conductive pillars provided within the semiconductive material layer, the pair of pillars being separated from one another and thereby having a mass of the semiconductive material extending therebetween; and iii) an electrically conductive node in electrical connection with each of the respective conductive pillars. Alternately, a resistor is provided within a semiconductive substrate using different concentration diffusion regions.
摘要翻译：从半导体材料形成电阻器的方法包括：a）提供衬底; b）在衬底上提供半导体材料层; c）在半导体材料层中提供一对开口; d）用导电材料堵塞所述一对开口，以在所述半导体材料内限定一对导电柱，所述一对支柱具有在其间延伸的半导体材料以提供电阻器结构; 以及e）为每个导电柱提供导电节点。结合电阻器结构的集成电路包括：i）半导体材料层; ii）设置在半导体材料层内的一对导电柱，所述一对柱彼此分离，从而具有在其间延伸的半导体材料的质量; 以及iii）与每个相应的导电柱电连接的导电节点。或者，使用不同的浓度扩散区域在半导体衬底内提供电阻器。

89. 发明授权

US05998256A Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry 失效
公开(公告)号：US05998256A
公开(公告)日：1999-12-07
申请号：US742895
申请日：1996-11-01
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L21/02 , H01L21/033 , H01L21/8242 , H01L27/02 , H01L27/108
CPC分类号： H01L27/1085 , H01L21/0331 , H01L28/40 , H01L27/0207 , H01L27/10808 , Y10S438/947
摘要： Semiconductor processing methods include forming a plurality of patterned device outlines over a semiconductor substrate, forming electrically insulative partitions or spacers on at least a portion of the patterned device outlines, and forming a plurality of substantially identically shaped devices relative to the patterned device outlines. Individual formed devices are spaced from at least one other of the devices by a distance no more than a width of one of the electrically insulative spacers. In such manner, device pitch is reduced by almost fifty percent. According to one aspect, elongated electrically conductive lines are formed. According to another aspect, capacitors are formed which, according to a preferred embodiment form part of a dynamic random access memory (DRAM) array.

90. 发明授权

US5923078A Method of forming a resistor and integrated circuitry having a resistor construction 失效
公开(公告)号：US5923078A
公开(公告)日：1999-07-13
申请号：US079368
申请日：1998-05-15
申请人： Kirk Prall , Pierre C. Fazan , Aftab Ahmad , Howard E. Rhodes , Werner Juengling , Pai-Hung Pan , Tyler Lowrey
发明人： Kirk Prall , Pierre C. Fazan , Aftab Ahmad , Howard E. Rhodes , Werner Juengling , Pai-Hung Pan , Tyler Lowrey
IPC分类号： H01L21/329 , H01L27/06 , H01L27/08 , H01L29/00
CPC分类号： H01L29/66166 , H01L27/0629 , H01L27/0802
摘要： A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars. An integrated circuit incorporating a resistor construction includes, i) a layer of semiconductive material; ii) a pair of electrically conductive pillars provided within the semiconductive material layer, the pair of pillars being separated from one another and thereby having a mass of the semiconductive material extending therebetween; and iii) an electrically conductive node in electrical connection with each of the respective conductive pillars. Alternately, a resistor is provided within a semiconductive substrate using different concentration diffusion regions.

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