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81. 发明申请

US20060284519A1 Sound-electricity conversion device, array-type ultrasonic transducer, and ultrasonic diagnostic apparatus 有权
标题翻译：声电转换装置，阵列式超声波换能器和超声波诊断装置
公开(公告)号：US20060284519A1
公开(公告)日：2006-12-21
申请号：US11341655
申请日：2006-01-30
申请人： Shinichiro Umemura , Takashi Azuma , Tatsuya Nagata , Hiroshi Fukuda , Toshiyuki Mine , Syuntaro Machida
发明人： Shinichiro Umemura , Takashi Azuma , Tatsuya Nagata , Hiroshi Fukuda , Toshiyuki Mine , Syuntaro Machida
IPC分类号： H01L41/00
CPC分类号： B06B1/0292
摘要： The present invention aims to stabilize sound-electricity conversion characteristics of a diaphragm-type sound-electricity conversion device as well as to decrease the noise level of an ultrasonic diagnostic apparatus using the sound-electricity conversion device. The sound-electricity conversion device is configured by a capacitor cell including a lower electrode formed on a silicon substrate and an upper electrode over the lower electrode, the lower and upper electrodes sandwiching a cavity. An electrode short-circuit prevention film is formed on the upper electrode on the cavity side. The electrode short-circuit prevention film is formed of a material with an electrical time constant shorter than 1 second and longer than 10 microseconds, such as silicon nitride containing a stoichiometrically excessive amount of silicon. As a result, the electrode short-circuit prevention film has small electric conductivity, and thus it is made possible to prevent the film from being charged with electric charge and to avoid the drift of the electric charge. Consequently, the sound-electricity conversion characteristics of the sound-electricity conversion device stabilize, and further the sound noise level of the ultrasonic diagnostic apparatus decreases.
摘要翻译：本发明旨在稳定隔膜式声电转换装置的声电转换特性，并且降低使用声电转换装置的超声波诊断装置的噪声水平。声电转换装置由包括形成在硅基板上的下电极和下电极上的上电极的电容器单元构成，下电极和上电极夹着空腔。在空腔侧的上部电极上形成电极短路防止膜。电极短路防止膜由电气时间常数短于1秒且长于10微秒的材料形成，例如含有化学计量过量的硅的氮化硅。结果，电极短路防止膜具有小的导电性，因此可以防止膜被充电并避免电荷的漂移。因此，声电转换装置的声电转换特性稳定，超声波诊断装置的声音噪声水平进一步降低。

82. 发明授权

US07132713B2 Controllable conduction device with electrostatic barrier 失效
标题翻译：带静电屏障的可控制传导装置
公开(公告)号：US07132713B2
公开(公告)日：2006-11-07
申请号：US10121596
申请日：2002-04-15
申请人： Kazuo Nakazato , Kiyoo Itoh , Hiroshi Mizuta , Toshikazu Shimada , Hideo Sunami , Tatsuya Teshima , Toshiyuki Mine , Ken Yamaguchi
发明人： Kazuo Nakazato , Kiyoo Itoh , Hiroshi Mizuta , Toshikazu Shimada , Hideo Sunami , Tatsuya Teshima , Toshiyuki Mine , Ken Yamaguchi
IPC分类号： H01L29/76 , H01L31/109
CPC分类号： H01L27/10858 , B82Y10/00 , G11C11/16 , H01L21/28273 , H01L27/10808 , H01L27/1082 , H01L27/10873 , H01L27/10876 , H01L27/11 , H01L29/154 , H01L29/42324 , H01L29/66825 , H01L29/772 , H01L29/78609 , H01L29/78618 , H01L29/78642 , H01L29/78687 , H01L29/7881 , H01L29/882
摘要： A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.
摘要翻译：晶体管形式的可控导电器件包括源极和漏极区域5，其间延伸用于电荷载流子的导电路径P，用于控制沿导电路径的电荷载流子的栅极4和提供多个导通路径中的隧道结结构，结果当晶体管处于其截止状态时，漏电流被多重隧道结构造阻塞。描述了垂直和横向晶体管配置，以及使用晶体管的互补对和随机存取存储器单元。描述了改进的栅极结构，其也适用于结合隧道势垒配置以在存储器节点上存储电荷的存储器件。

83. 发明授权

US07122900B2 Semiconductor device and method manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07122900B2
公开(公告)日：2006-10-17
申请号：US10276776
申请日：2001-05-28
申请人： Kenichi Takeda , Daisuke Ryuzaki , Kenji Hinode , Toshiyuki Mine
发明人： Kenichi Takeda , Daisuke Ryuzaki , Kenji Hinode , Toshiyuki Mine
IPC分类号： H01L21/44
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76811 , H01L21/76813
摘要： A semiconductor device according to this invention comprises a substrate 100 in which semiconductor elements are formed, a first conductor 301 at least a portion of the peripheral surface of which is made of a material comprising copper as a main ingredient, and a first insulative diffusion barrier layer 203 covering at least a portion of the first conductor 301. The first insulative diffusion barrier layer 203 is formed by using a gas mixture at least containing an alkoxy silane represented by the general formula (RO)nSiH4−n (n is an integer in a range from 1 to 3, R represents an alkyl group, an aryl group or a derivative thereof), and an oxidative gas by a plasma CVD. Thus, a semiconductor device comprising copper wiring of high reliability and with less wiring delay time can be provided.
摘要翻译：根据本发明的半导体器件包括其中形成有半导体元件的基板100，其外围表面的至少一部分由包含铜作为主要成分的材料制成的第一导体301和第一绝缘扩散阻挡层层203覆盖第一导体301的至少一部分。第一绝缘扩散阻挡层203通过使用至少含有由通式（RO）表示的烷氧基硅烷的气体混合物形成（n为 1〜3的整数，R表示烷基，芳基或其衍生物）和通过等离子体CVD的氧化性气体。因此，可以提供包括具有高可靠性和较少布线延迟时间的铜布线的半导体器件。

84. 发明授权

US07064400B2 Semiconductor device and process for producing the same 失效
公开(公告)号：US07064400B2
公开(公告)日：2006-06-20
申请号：US11000992
申请日：2004-12-02
申请人： Jiro Yugami , Natsuki Yokoyama , Toshiyuki Mine , Yasushi Goto
发明人： Jiro Yugami , Natsuki Yokoyama , Toshiyuki Mine , Yasushi Goto
IPC分类号： H01L29/76
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/28114 , H01L21/28176 , H01L21/28185 , H01L21/823418 , H01L21/823425 , H01L21/823456 , H01L21/823462 , H01L29/42368 , H01L29/495 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78
摘要： There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.

85. 发明申请

US20060051977A1 Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device 有权
公开(公告)号：US20060051977A1
公开(公告)日：2006-03-09
申请号：US11266430
申请日：2005-11-04
申请人： Tetsuo Adachi , Masataka Kato , Toshiaki Nishimoto , Nozomu Matsuzaki , Takashi Kobayashi , Yoshimi Sudou , Toshiyuki Mine
发明人： Tetsuo Adachi , Masataka Kato , Toshiaki Nishimoto , Nozomu Matsuzaki , Takashi Kobayashi , Yoshimi Sudou , Toshiyuki Mine
IPC分类号： H01L21/31
CPC分类号： H01L21/28273 , G11C11/5628 , G11C16/0466 , G11C16/10 , G11C16/3454 , H01L21/28061 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11536 , H01L27/11546 , H01L29/6659 , H01L29/66825 , H01L29/7833
摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

86. 发明申请

US20050212082A1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050212082A1
公开(公告)日：2005-09-29
申请号：US11059651
申请日：2005-02-17
申请人： Kenichi Takeda , Tsuyoshi Fujiwara , Toshinori Imai , Tsuyoshi Ishikawa , Toshiyuki Mine , Makoto Miura
发明人： Kenichi Takeda , Tsuyoshi Fujiwara , Toshinori Imai , Tsuyoshi Ishikawa , Toshiyuki Mine , Makoto Miura
IPC分类号： H01L21/02 , H01L21/768 , H01L27/108
CPC分类号： H01L28/40 , H01L21/76838
摘要： An MIM capacitor using a high-permittivity dielectric film such as tantalum oxide. The MIM capacitor includes an upper electrode, a dielectric film, and a lower electrode. A second dielectric film and the dielectric film are formed between the upper electrode and the lower electrode, at the end of the MIM capacitor. The second dielectric film is formed to have an opening at the top of the lower electrode. The dielectric film abuts the lower electrode via the opening. The upper electrode is formed on the dielectric film. The upper electrode and the dielectric film are formed in such a manner as to embrace the opening entirely, and the second dielectric film and the lower electrode are formed so that the respective widths are the same as, or greater than, the widths of the upper electrode and the dielectric film.
摘要翻译：使用诸如氧化钽的高介电常数电介质膜的MIM电容器。 MIM电容器包括上电极，电介质膜和下电极。在MIM电容器的端部，在上电极和下电极之间形成第二电介质膜和电介质膜。第二电介质膜形成为在下电极的顶部具有开口。电介质膜经由开口抵接下电极。上电极形成在电介质膜上。上部电极和电介质膜以完全包围开口的方式形成，并且第二电介质膜和下部电极形成为使得各个宽度与上部的宽度相同或更大电极和电介质膜。

87. 发明申请

US20050189579A1 Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device 有权
公开(公告)号：US20050189579A1
公开(公告)日：2005-09-01
申请号：US11107826
申请日：2005-04-18
申请人： Tetsuo Adachi , Masataka Kato , Toshiaki Nishimoto , Nozomu Matsuzaki , Takashi Kobayashi , Yoshimi Sudou , Toshiyuki Mine
发明人： Tetsuo Adachi , Masataka Kato , Toshiaki Nishimoto , Nozomu Matsuzaki , Takashi Kobayashi , Yoshimi Sudou , Toshiyuki Mine
IPC分类号： H01M10/0525 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/34 , G11C27/00 , H01L21/00 , H01L21/28 , H01L21/283 , H01L21/336 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/76 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/94 , H01L31/062 , H01L31/119 , H01M2/16
CPC分类号： H01L21/28273 , G11C11/5628 , G11C16/0466 , G11C16/10 , G11C16/3454 , H01L21/28061 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11536 , H01L27/11546 , H01L29/6659 , H01L29/66825 , H01L29/7833
摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

88. 发明申请

US20050098823A1 Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device 有权
标题翻译：非易失性半导体存储器及其制造方法，以及半导体器件及其制造方法
公开(公告)号：US20050098823A1
公开(公告)日：2005-05-12
申请号：US10954096
申请日：2004-09-30
申请人： Tetsuo Adachi , Yoshimi Sudou , Toshiyuki Mine
发明人： Tetsuo Adachi , Yoshimi Sudou , Toshiyuki Mine
IPC分类号： H01M10/0525 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/34 , G11C27/00 , H01L21/00 , H01L21/28 , H01L21/283 , H01L21/336 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/76 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/94 , H01L31/062 , H01L31/119 , H01M2/16
CPC分类号： H01L21/28273 , G11C11/5628 , G11C16/0466 , G11C16/10 , G11C16/3454 , H01L21/28061 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11536 , H01L27/11546 , H01L29/6659 , H01L29/66825 , H01L29/7833
摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
摘要翻译：一种半导体器件，其特别是确保器件的可靠性，特别是在微细的区域中并且能够实现大的电容和高速操作，具有在半导体衬底的主表面的第一区域中包括栅绝缘膜，浮栅电极，层间绝缘膜，控制栅极电极以及以矩阵形式布置的第二导电类型的源极和漏极区域，具有用于隔离存储单元的浅隔离结构。当使用用绝缘膜掩埋的浅结构用于元件隔离时，可以防止微细区域中的隔离耐受电压降低，并且可以降低选择性晶体管的阈值电平的变化。当通过选择性晶体管分配存储器垫中的存储单元时，可以提高存储单元的干扰电阻。

89. 发明授权

US06876023B2 Gain cell type non-volatile memory having charge accumulating region charged or discharged by channel current from a thin film channel path 失效
标题翻译：具有从薄膜通道路径通过通道电流充电或放电的电荷累积区域的增益单元型非易失性存储器
公开(公告)号：US06876023B2
公开(公告)日：2005-04-05
申请号：US10158851
申请日：2002-06-03
申请人： Tomoyuki Ishii , Kazuo Yano , Toshiyuki Mine
发明人： Tomoyuki Ishii , Kazuo Yano , Toshiyuki Mine
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/8242 , H01L21/8244 , H01L27/105 , H01L27/108 , H01L27/11 , H01L27/115 , H01L27/12 , H01L29/66 , H01L29/786 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0433 , H01L27/105 , H01L27/108 , H01L27/10873 , H01L27/12 , H01L27/1203 , H01L29/78642
摘要： A semiconductor memory element subject to a threshold voltage controlling method other than those based on low leak currents or on the implantation of impurities. Such semiconductor elements are used to form semiconductor memory elements that are employed in scaled-down structures and are conducive to high-speed write operations thanks to a sufficiently prolonged refresh cycle. These semiconductor memory elements are in turn used to constitute a semiconductor memory device. A very thin semiconductor film is used as channels so that leak currents are reduced by the quantum-mechanical containment effect in the direction of film thickness. An amount of electrical charges in each charge accumulating region is used to change conductance between a source and a drain region of each read transistor structure, the conductance change being utilized for data storage. A channel of a transistor for electrically charging or discharging each charge accumulating region is made of a semiconductor film 5 nm thick at most. The arrangement affords both high-speed data write performance and an extended data retention time. The invention provides a high-speed, power-saving semiconductor device of high integration particularly advantageous for producing a small-scale system of low-power dissipation.
摘要翻译：除了基于低泄漏电流或杂质注入以外的阈值电压控制方法的半导体存储元件。这样的半导体元件用于形成在缩小结构中使用的半导体存储器元件，并且由于足够长的刷新周期而有利于高速写入操作。这些半导体存储元件又用于构成半导体存储器件。使用非常薄的半导体膜作为通道，使得通过膜厚度方向的量子力学容纳效应来降低泄漏电流。使用每个电荷累积区域中的电荷量来改变每个读取晶体管结构的源区和漏区之间的电导，所述电导变化用于数据存储。用于对每个电荷累积区进行充电或放电的晶体管的沟道由最多为5nm厚的半导体膜制成。该方案具有高速数据写入性能和扩展数据保留时间。本发明提供了高集成度的高速，省电的半导体器件，特别有利于生产低功耗的小规模系统。

90. 发明授权

US06849513B2 Semiconductor device and production method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06849513B2
公开(公告)日：2005-02-01
申请号：US10683387
申请日：2003-10-14
申请人： Shimpei Tsujikawa , Jiro Yugami , Toshiyuki Mine , Masahiro Ushiyama
发明人： Shimpei Tsujikawa , Jiro Yugami , Toshiyuki Mine , Masahiro Ushiyama
IPC分类号： H01L29/78 , H01L21/28 , H01L29/51 , H01L21/336
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/511 , H01L29/513 , H01L29/518
摘要： The present invention provides a MOS semiconductor device which enables gate leakage current reduction with a thinner gate dielectric film for higher speed, and a production method thereof. According to the present invention, a gate dielectric film 6 is made as follows: after forming a silicon nitride film 3 with a specified thickness, it is annealed in an oxidizing atmosphere to form silicon oxide 4 on the silicon nitride film 3, then this silicon oxide 4 is completely removed by exposure to a dissolving liquid. As a result, at depths between 0.12 nm and 0.5 nm from the top surface of the silicon nitride film 3 in the gate dielectric film 6 whose main constituent elements are silicon, nitrogen and oxygen, the nitrogen concentration is higher than the oxygen concentration. This enables the use of a thinner gate dielectric film with silicon, nitrogen and oxygen as main constituent elements while at the same time realizing reduction in leakage currents.
摘要翻译：本发明提供一种能够通过较薄栅极电介质膜进行栅极泄漏电流降低的MOS半导体器件及其制造方法。根据本发明，栅电介质膜6如下制作：在形成规定厚度的氮化硅膜3之后，在氧化气氛中进行退火，在氮化硅膜3上形成氧化硅4，氧化物4通过暴露于溶解液而完全除去。结果，在主要构成元素为硅，氮和氧的栅极电介质膜6中，距离氮化硅膜3的顶表面在0.12nm至0.5nm之间的深度处，氮浓度高于氧浓度。这使得能够使用具有硅，氮和氧作为主要构成元件的较薄的栅极电介质膜，同时实现漏电流的减小。

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