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81. 发明申请

US20090077155A1 HIGH SPEED ADDER DESIGN FOR A MULTIPLY-ADD BASED FLOATING POINT UNIT 失效
标题翻译：用于基于多媒体增量浮动点单元的高速加法器设计
公开(公告)号：US20090077155A1
公开(公告)日：2009-03-19
申请号：US12323257
申请日：2008-11-25
申请人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/50
CPC分类号： G06F7/483 , G06F7/5443
摘要： A method is provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.
摘要翻译：提供了一种用于在给定计算机系统中改进浮点单元（FPU）的高速加法器的方法。改进的加法器利用复合增量器，复合加法器，进位网络，加法器控制/选择器和多路复用器（多路复用器）系列。进位网络同时执行终结进位功能，并且独立于优化加法器功能的其他所需功能。此外，还使用最小数量的多路复用器来减少多路复用器延迟。

82. 发明申请

US20070300082A1 Method for controlling operation of microprocessor which performs duty cycle correction process 失效
标题翻译：用于控制执行占空比校正处理的微处理器的操作的方法
公开(公告)号：US20070300082A1
公开(公告)日：2007-12-27
申请号：US11471819
申请日：2006-06-21
申请人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry , Sang Hoo Dhong
发明人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry , Sang Hoo Dhong
IPC分类号： G06F1/00
CPC分类号： G06F1/04
摘要： A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.
摘要翻译：用于向微处理器提供电源电压的技术。在微处理器的正常运算处理之前，执行用于调整微处理器内的时钟信号占空比的占空比校正处理。在用于调整占空比的占空比校正处理中，调整时钟信号的占空比以使微处理器仍然可操作的电源电压最小化。

83. 发明授权

US07245159B2 Protecting one-hot logic against short-circuits during power-on 失效
标题翻译：保护开机时防止短路的单热逻辑
公开(公告)号：US07245159B2
公开(公告)日：2007-07-17
申请号：US10891771
申请日：2004-07-15
申请人： Sang Hoo Dhong , Christian Jacobi , Hwa-Joon Oh , Silvia Melitta Mueller
发明人： Sang Hoo Dhong , Christian Jacobi , Hwa-Joon Oh , Silvia Melitta Mueller
IPC分类号： H03K19/20
CPC分类号： H03K17/223 , H03K17/005
摘要： A method, a computer program, and an apparatus are provided to protect transmission gates in a multiplexer (mux). Because transmission gates are much faster than the more convention AND-OR arrays, transmission gate usage in muxes are being used more often in high speed circuitry. However, transmission gate have a significant problem in that short circuit are possible for situations where there is not a one-hot select signal. Therefore, to eliminate the problem, logic gates are utilized specifically during Power-On Reset (POR) to force a one-hot selection to prevent any possible short circuits.
摘要翻译：提供了一种方法，计算机程序和装置来保护复用器（多路复用器）中的传输门。因为传输门比更常规的AND-OR阵列快得多，所以在高速电路中更频繁地使用多路复用器中的传输门使用。然而，传输门具有显着的问题，即在没有单热选择信号的情况下短路是可能的。因此，为了消除这个问题，在上电复位（POR）期间特别使用逻辑门来强制单热选择以防止任何可能的短路。

84. 发明授权

US07058830B2 Power saving in a floating point unit using a multiplier and aligner bypass 失效
标题翻译：使用乘法器和对准器旁路在浮点单元中节电
公开(公告)号：US07058830B2
公开(公告)日：2006-06-06
申请号：US10392764
申请日：2003-03-19
申请人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh , Kevin Duc Tran
发明人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh , Kevin Duc Tran
IPC分类号： G06F1/32
CPC分类号： G06F9/30014 , G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F7/483 , G06F2207/3868 , Y02D10/128 , Y02D10/152 , Y02D10/171
摘要： The present invention provides for saving power in a floating point unit. Bypass logic is coupled to the input of the aligner and the multiplier. An aligner bypass is coupled to the output of the aligner and an output of the bypass logic. A multiplier bypass is coupled to the output of the multiplier and an output of the bypass logic. The aligner bypass and the multiplier bypass transmit the output of the aligner and multiplier, or the bypass logic, as a function of an aligner bypass signal and a multiplier bypass signal, respectively. An adder is coupled to the output of the aligner bypass and the multiplier bypass. Clock disable logic is used to selectively enable and disable at least portions of the aligner, multiplier and bypass logic. This is done based on the operation and on the value of the operands.
摘要翻译：本发明提供了一种在浮点单元中节省功率的方法。旁路逻辑耦合到对准器和乘法器的输入。对准器旁路耦合到对准器的输出和旁路逻辑的输出。乘法器旁路耦合到乘法器的输出和旁路逻辑的输出。对准器旁路和乘法器旁路分别作为对准器旁路信号和乘法器旁路信号的函数传输对准器和乘法器或旁路逻辑的输出。加法器耦合到对准器旁路和乘法器旁路的输出端。时钟禁止逻辑用于选择性地启用和禁用对准器，乘法器和旁路逻辑的至少一部分。这是基于操作和操作数的值完成的。

85. 发明申请

US20050086279A1 Methods and apparatus for performing multi-value range checks 失效
标题翻译：执行多值范围检查的方法和装置
公开(公告)号：US20050086279A1
公开(公告)日：2005-04-21
申请号：US10687437
申请日：2003-10-16
申请人： Sang Hoo Dhong , Silvia Mueller , Hiroo Nishikawa , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Silvia Mueller , Hiroo Nishikawa , Hwa-Joon Oh
IPC分类号： G06F5/01 , G06F7/02 , G06F7/42 , G06F7/485
CPC分类号： G06F7/026 , G06F5/012 , G06F7/485
摘要： In a first aspect, a method is provided for determining in which of n intervals a sum of two or more numbers resides. The method includes determining the two or more numbers, and providing fewer than n compress circuits each adapted to (1) input the two or more numbers; (2) input range information regarding ranges used to define the n intervals; and (3) compress the two or more numbers and the range information into two or more outputs. The method further includes employing the fewer than n compress circuits to determine in which of the n intervals the sum of the two or more numbers resides. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种用于确定n个间隔中的哪一个是两个或多个数字的和的位置的方法。该方法包括确定两个或多个数字，并且提供少于n个压缩电路，每个压缩电路适于（1）输入两个或多个数字; （2）关于用于定义n个间隔的范围的输入范围信息; 和（3）将两个以上的数字和范围信息压缩成两个以上的输出。该方法还包括采用少于n个压缩电路来确定n个间隔中的哪一个是两个或多个数字的和。提供了许多其他方面。

86. 发明授权

US06760819B2 Symmetric multiprocessor coherence mechanism 有权
标题翻译：对称多处理器一致性机制
公开(公告)号：US06760819B2
公开(公告)日：2004-07-06
申请号：US09895888
申请日：2001-06-29
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Charles Ray Johns , John Samuel Liberty , Thuong Quang Truong
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Charles Ray Johns , John Samuel Liberty , Thuong Quang Truong
IPC分类号： G06F1208
CPC分类号： G06F12/0822 , G06F12/0811 , G06F12/084
摘要： A processor-cache operational scheme and topology within a multi-processor data processing system having a shared lower level cache (or memory) by which the number of coherency busses is reduced and more efficient snoop resolution and coherency operations with the processor caches are provided. A copy of the internal (L1) cache directory is provided within the lower level (L2) cache or memory. The snoop operations and coherency maintenance operations of the L1 directory are completed by comparing the snoop addresses with the address tags of the copy of the L1 directory in the L2 cache. Updates to the coherency states of the copy of the L1 directory are mirrored in the L1 directory and L1 cache. This eliminates the need for the individual coherency buses of each processor that is coupled to the L2 cache and speeds up coherency operations because the snoops do not have to be transmitted to the L1 caches.
摘要翻译：提供具有共享低级高速缓存（或存储器）的多处理器数据处理系统中的处理器 - 高速缓存操作方案和拓扑，通过该共享低级高速缓存（或存储器）减少一致性总线的数量并且提供与处理器高速缓存更有效的窥探分辨率和一致性操作。在低级（L2）高速缓存或内存中提供内部（L1）缓存目录的副本。通过将侦听地址与L2缓存中L1目录的副本的地址标签进行比较，完成L1目录的侦听操作和一致性维护操作。对L1目录的副本的一致性状态的更新被镜像在L1目录和L1缓存中。这消除了对耦合到L2高速缓存的每个处理器的各个一致性总线的需要，并且加速一致性操作，因为该探测不必被传送到L1高速缓存。

87. 发明授权

US06587388B2 Method and apparatus for reducing write operation time in dynamic random access memories 失效
公开(公告)号：US06587388B2
公开(公告)日：2003-07-01
申请号：US09844837
申请日：2001-04-27
申请人： Toshiaki Kirihata , Sang Hoo Dhong , Hwa-Joon Oh
发明人： Toshiaki Kirihata , Sang Hoo Dhong , Hwa-Joon Oh
IPC分类号： G11C700
CPC分类号： G11C7/22 , G11C11/4076
摘要： A method for preparing a dynamic random access memory (DRAM) cell for a write operation with a preset condition is disclosed. In an exemplary embodiment, the method includes creating a preset voltage level within the cell prior to a delayed write back in a destructive read architecture, which preset voltage level has a value between a logic 0 voltage level and a logic 1 voltage level. The logic 0 voltage level corresponds to a first cell voltage value when the cell has a 0 bit stored therein, and the logic 1 voltage level corresponds to a second cell voltage value when the cell has a 1 bit stored therein. Prior to the creation of the preset voltage level within the cell, the cell has an initial voltage value corresponding to either the logic 0 voltage level or the logic 1 voltage level.

88. 发明授权

US06510093B1 Method and apparatus for cycle time reduction in a memory system using alternating reference cells and isolated sense lines 失效
标题翻译：使用交替参考单元和隔离感测线的存储器系统中的周期时间减少的方法和装置
公开(公告)号：US06510093B1
公开(公告)日：2003-01-21
申请号：US09982163
申请日：2001-10-18
申请人： Sang Hoo Dhong , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Hwa-Joon Oh
IPC分类号： G11C700
CPC分类号： G11C7/12 , G11C7/14 , G11C11/4076 , G11C11/4094 , G11C11/4099
摘要： In one aspect, reading a memory includes conductively coupling a memory cell and a first reference cell to respective lines of a selected bit line pair for a voltage development interval. During the interval a voltage differential develops on the bit line pair and is transmitted to a corresponding sense line pair. A second reference cell is precharged for the selected bit line pair for a reference cell precharging interval, the reference cell precharging interval being concurrent with at least a portion of the voltage development interval. A sense amplifier is enabled for a voltage detection interval. The bit line pair is precharged for a bit line precharging interval. The sense line pair is isolated from the bit line pair during the bit line precharging interval and the bit line precharging interval is concurrent with at least a portion of the voltage detection interval.
摘要翻译：在一个方面，读取存储器包括将存储器单元和第一参考单元导电地耦合到用于电压发展间隔的所选位线对的各个线。在间隔期间，位线对上产生电压差，并传输到相应的感测线对。对于所选择的位线对，对于参考单元预充电间隔，第二参考单元被预充电，所述参考单元预充电间隔与所述电压显影间隔的至少一部分同时。读出放大器使能电压检测间隔。对于位线预充电间隔，位线对被预充电。在位线预充电间隔期间，感测线对与位线对隔离，并且位线预充电间隔与电压检测间隔的至少一部分同时发生。

89. 发明授权

US06232872B1 Comparator 失效
标题翻译：比较器
公开(公告)号：US06232872B1
公开(公告)日：2001-05-15
申请号：US09418377
申请日：1999-10-14
申请人： Sang Hoo Dhong , Hung Cai Ngo , Jaehong Park
发明人： Sang Hoo Dhong , Hung Cai Ngo , Jaehong Park
IPC分类号： G06F702
CPC分类号： G06F7/026 , G06F12/0895
摘要： A 64-bit comparator includes a first stage for receiving a 64-bit number A and a 64-bit number B, and generating first output values. A second stage then receives the first output values from the first stage and outputs second output values, and a third stage receives the second output values from the second stage and outputs greater than, less than, and equivalent values. Thus, the comparator is faster in that it is implemented in three logic stages by making efficient use of compound dynamic gates.
摘要翻译： 64位比较器包括用于接收64位数字A和64位数字B的第一级，并且产生第一输出值。然后，第二级接收来自第一级的第一输出值并输出第二输出值，第三级从第二级接收第二输出值，并输出大于，小于和等效的值。因此，比较器更快，因为它通过有效地使用复合动态门在三个逻辑阶段中被实现。

90. 发明授权

US08229989B2 Method for controlling rounding modes in single instruction multiple data (SIMD) floating-point units 有权
标题翻译：用于控制单指令多数据（SIMD）浮点单元中舍入模式的方法
公开(公告)号：US08229989B2
公开(公告)日：2012-07-24
申请号：US12238500
申请日：2008-09-26
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/38
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49968 , G06F7/49973 , G06F7/49989 , G06F2207/3828
摘要： A method for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.
摘要翻译：公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的方法。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。

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