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1. 发明授权

US07447725B2 Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units 失效
标题翻译：用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置
公开(公告)号：US07447725B2
公开(公告)日：2008-11-04
申请号：US10982110
申请日：2004-11-05
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/38
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49968 , G06F7/49973 , G06F7/49989 , G06F2207/3828
摘要： An apparatus for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.
摘要翻译：公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。

2. 发明授权

US07406589B2 Processor having efficient function estimate instructions 失效
标题翻译：处理器具有有效的功能估计指令
公开(公告)号：US07406589B2
公开(公告)日：2008-07-29
申请号：US11127848
申请日：2005-05-12
申请人： Sang Hoo Dhong , Gordon Clyde Fossum , Harm Peter Hofstee , Brad William Michael , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Gordon Clyde Fossum , Harm Peter Hofstee , Brad William Michael , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/552 , G06F7/544 , G06F7/38
CPC分类号： G06F7/483 , G06F7/535 , G06F7/5443 , G06F7/5525 , G06F9/30014 , G06F2207/5356
摘要： High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.
摘要翻译：高精度浮点函数估计分为两个指令：低精度表查找指令和线性插值指令。可以使用该方案来实现不同功能的估计：为每个不同的功能提供单独的表查找指令，而仅需要单个插补指令，因为单个内插指令可以执行任何功能的内插步骤估计。因此，与专用硬件相比，产生的开销大大降低，同时仍保持统一的FPU延迟，这允许更简单的控制逻辑。

3. 发明授权

US07237163B2 Leakage current reduction system and method 有权
标题翻译：漏电流减少系统及方法
公开(公告)号：US07237163B2
公开(公告)日：2007-06-26
申请号：US10982111
申请日：2004-11-05
申请人： Sang Hoo Dhong , Hwa-Joon Oh , Silvia Melitta Mueller , Joel Silberman
发明人： Sang Hoo Dhong , Hwa-Joon Oh , Silvia Melitta Mueller , Joel Silberman
IPC分类号： G01R31/28
CPC分类号： G06F11/267 , G01R31/3008
摘要： An apparatus, a method and a computer program are provided to reduce leakage current in a processor. Traditionally, extra logic is employed to reduce leakage currents. However, reducing leakage current without sacrificing fine grain operations and speed can be difficult. Achieving such a goal can be accomplished by incorporating a multiplexer (mux) into the scan-in path of scan registers so that units or sub-units of the processor can be powered down individually. Additionally, the muxes are not incorporated into time paths, so speed can be preserved.
摘要翻译：提供了一种装置，方法和计算机程序以减少处理器中的泄漏电流。传统上，采用额外的逻辑来减少漏电流。然而，减少泄漏电流而不牺牲精细的晶粒操作和速度可能是困难的。可以通过将多路复用器（多路复用器）复用到扫描寄存器的扫描路径中来实现这一目标，从而可以单独关闭处理器的单元或子单元。此外，多路复用器并不并入时间路径，因此可以保留速度。

4. 发明授权

US07149877B2 Byte execution unit for carrying out byte instructions in a processor 失效
标题翻译：用于在处理器中执行字节指令的字节执行单元
公开(公告)号：US07149877B2
公开(公告)日：2006-12-12
申请号：US10621908
申请日：2003-07-17
申请人： Sang Hoo Dhong , Hwa-Joon Oh , Brad William Michael , Silvia Melitta Mueller , Kevin D. Tran
发明人： Sang Hoo Dhong , Hwa-Joon Oh , Brad William Michael , Silvia Melitta Mueller , Kevin D. Tran
IPC分类号： G06F15/76
CPC分类号： G06F9/30014 , G06F9/30036
摘要： A disclosed byte execution unit receives byte instruction information and two operands, and performs an operation specified by the byte instruction information upon one or both of the operands, thereby producing a result. The byte instruction specifies either a count ones in bytes operation, an average bytes operation, an absolute differences of bytes operation, or a sum bytes into halfwords operation. In one embodiment, the byte execution unit includes multiple byte units. Each byte unit includes multiple population counters, two compressor units, adder input multiplexer logic, adder logic, and result multiplexer logic. A data processing system is described including a processor coupled to a memory system. The processor includes the byte execution unit. The memory system includes a byte instruction, wherein the byte instruction specifies either the count ones in bytes operation, the average bytes operation, the absolute differences of bytes operation, or the sum bytes into halfwords operation.
摘要翻译：公开的字节执行单元接收字节指令信息和两个操作数，并且在一个或两个操作数上执行由字节指令信息指定的操作，从而产生结果。字节指令指定以字节为单位的计数值，平均字节操作，字节操作的绝对差值，或字节字节到半字操作。在一个实施例中，字节执行单元包括多个字节单元。每个字节单元包括多个总体计数器，两个压缩器单元，加法器输入复用器逻辑，加法器逻辑和结果复用器逻辑。描述了包括耦合到存储器系统的处理器的数据处理系统。处理器包括字节执行单元。存储器系统包括一个字节指令，其中字节指令指定字节操作中的计数值，平均字节操作，字节操作的绝对差值，或字节数字到半字操作。

5. 发明授权

US06829682B2 Destructive read architecture for dynamic random access memories 有权
标题翻译：用于动态随机存取存储器的破坏性读取架构
公开(公告)号：US06829682B2
公开(公告)日：2004-12-07
申请号：US09843504
申请日：2001-04-26
申请人： Toshiaki Kirihata , Sang Hoo Dhong , Hwa-Joon Oh , Matthew Wordeman
发明人： Toshiaki Kirihata , Sang Hoo Dhong , Hwa-Joon Oh , Matthew Wordeman
IPC分类号： G06F1200
CPC分类号： G06F12/0893 , G11C7/1006 , G11C2207/2245
摘要： A method for controlling the operation of a dynamic random access memory (DRAM) system, the DRAM system having a plurality of memory cells organized into rows and columns, is disclosed. In an exemplary embodiment of the invention, the method includes enabling a destructive read mode, the destructive read mode for destructively reading a bit of information stored within an addressed DRAM memory cell. The destructively read bit of information is temporarily stored into a temporary storage device. A delayed write back mode is enabled, the delayed write back mode for restoring the bit of information back to the addressed DRAM memory cell at a later time. The execution of the delayed write back mode is then scheduled, depending upon the availability of space within the temporary storage device.
摘要翻译：公开了一种用于控制动态随机存取存储器（DRAM）系统的操作的方法，该DRAM系统具有被组织成行和列的多个存储单元。在本发明的示例性实施例中，该方法包括启用破坏性读取模式，该破坏性读取模式用于破坏性地读取存储在寻址的DRAM存储器单元中的位的位。信息的破坏性读取位被临时存储到临时存储设备中。延迟回写模式被使能，延迟回写模式用于将信息位在稍后的时间恢复到寻址的DRAM存储器单元。然后根据临时存储设备内的空间的可用性来调度延迟写回模式的执行。

6. 发明授权

US08131795B2 High speed adder design for a multiply-add based floating point unit 失效
标题翻译：用于基于加法的浮点单元的高速加法器设计
公开(公告)号：US08131795B2
公开(公告)日：2012-03-06
申请号：US12323257
申请日：2008-11-25
申请人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/42 , G06F7/38
CPC分类号： G06F7/483 , G06F7/5443
摘要： A method is provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.
摘要翻译：提供了一种用于在给定计算机系统中改进浮点单元（FPU）的高速加法器的方法。改进的加法器利用复合增量器，复合加法器，进位网络，加法器控制/选择器和多路复用器（多路复用器）系列。进位网络同时执行结束进位功能并且独立于优化加法器功能的其他所需功能。此外，还使用最小数量的多路复用器来减少多路复用器延迟。

7. 发明申请

US20090077155A1 HIGH SPEED ADDER DESIGN FOR A MULTIPLY-ADD BASED FLOATING POINT UNIT 失效
标题翻译：用于基于多媒体增量浮动点单元的高速加法器设计
公开(公告)号：US20090077155A1
公开(公告)日：2009-03-19
申请号：US12323257
申请日：2008-11-25
申请人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/50
CPC分类号： G06F7/483 , G06F7/5443
摘要： A method is provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.
摘要翻译：提供了一种用于在给定计算机系统中改进浮点单元（FPU）的高速加法器的方法。改进的加法器利用复合增量器，复合加法器，进位网络，加法器控制/选择器和多路复用器（多路复用器）系列。进位网络同时执行终结进位功能，并且独立于优化加法器功能的其他所需功能。此外，还使用最小数量的多路复用器来减少多路复用器延迟。

8. 发明授权

US07245159B2 Protecting one-hot logic against short-circuits during power-on 失效
标题翻译：保护开机时防止短路的单热逻辑
公开(公告)号：US07245159B2
公开(公告)日：2007-07-17
申请号：US10891771
申请日：2004-07-15
申请人： Sang Hoo Dhong , Christian Jacobi , Hwa-Joon Oh , Silvia Melitta Mueller
发明人： Sang Hoo Dhong , Christian Jacobi , Hwa-Joon Oh , Silvia Melitta Mueller
IPC分类号： H03K19/20
CPC分类号： H03K17/223 , H03K17/005
摘要： A method, a computer program, and an apparatus are provided to protect transmission gates in a multiplexer (mux). Because transmission gates are much faster than the more convention AND-OR arrays, transmission gate usage in muxes are being used more often in high speed circuitry. However, transmission gate have a significant problem in that short circuit are possible for situations where there is not a one-hot select signal. Therefore, to eliminate the problem, logic gates are utilized specifically during Power-On Reset (POR) to force a one-hot selection to prevent any possible short circuits.
摘要翻译：提供了一种方法，计算机程序和装置来保护复用器（多路复用器）中的传输门。因为传输门比更常规的AND-OR阵列快得多，所以在高速电路中更频繁地使用多路复用器中的传输门使用。然而，传输门具有显着的问题，即在没有单热选择信号的情况下短路是可能的。因此，为了消除这个问题，在上电复位（POR）期间特别使用逻辑门来强制单热选择以防止任何可能的短路。

9. 发明授权

US07058830B2 Power saving in a floating point unit using a multiplier and aligner bypass 失效
标题翻译：使用乘法器和对准器旁路在浮点单元中节电
公开(公告)号：US07058830B2
公开(公告)日：2006-06-06
申请号：US10392764
申请日：2003-03-19
申请人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh , Kevin Duc Tran
发明人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh , Kevin Duc Tran
IPC分类号： G06F1/32
CPC分类号： G06F9/30014 , G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F7/483 , G06F2207/3868 , Y02D10/128 , Y02D10/152 , Y02D10/171
摘要： The present invention provides for saving power in a floating point unit. Bypass logic is coupled to the input of the aligner and the multiplier. An aligner bypass is coupled to the output of the aligner and an output of the bypass logic. A multiplier bypass is coupled to the output of the multiplier and an output of the bypass logic. The aligner bypass and the multiplier bypass transmit the output of the aligner and multiplier, or the bypass logic, as a function of an aligner bypass signal and a multiplier bypass signal, respectively. An adder is coupled to the output of the aligner bypass and the multiplier bypass. Clock disable logic is used to selectively enable and disable at least portions of the aligner, multiplier and bypass logic. This is done based on the operation and on the value of the operands.
摘要翻译：本发明提供了一种在浮点单元中节省功率的方法。旁路逻辑耦合到对准器和乘法器的输入。对准器旁路耦合到对准器的输出和旁路逻辑的输出。乘法器旁路耦合到乘法器的输出和旁路逻辑的输出。对准器旁路和乘法器旁路分别作为对准器旁路信号和乘法器旁路信号的函数传输对准器和乘法器或旁路逻辑的输出。加法器耦合到对准器旁路和乘法器旁路的输出端。时钟禁止逻辑用于选择性地启用和禁用对准器，乘法器和旁路逻辑的至少一部分。这是基于操作和操作数的值完成的。

10. 发明申请

US20050086279A1 Methods and apparatus for performing multi-value range checks 失效
标题翻译：执行多值范围检查的方法和装置
公开(公告)号：US20050086279A1
公开(公告)日：2005-04-21
申请号：US10687437
申请日：2003-10-16
申请人： Sang Hoo Dhong , Silvia Mueller , Hiroo Nishikawa , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Silvia Mueller , Hiroo Nishikawa , Hwa-Joon Oh
IPC分类号： G06F5/01 , G06F7/02 , G06F7/42 , G06F7/485
CPC分类号： G06F7/026 , G06F5/012 , G06F7/485
摘要： In a first aspect, a method is provided for determining in which of n intervals a sum of two or more numbers resides. The method includes determining the two or more numbers, and providing fewer than n compress circuits each adapted to (1) input the two or more numbers; (2) input range information regarding ranges used to define the n intervals; and (3) compress the two or more numbers and the range information into two or more outputs. The method further includes employing the fewer than n compress circuits to determine in which of the n intervals the sum of the two or more numbers resides. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种用于确定n个间隔中的哪一个是两个或多个数字的和的位置的方法。该方法包括确定两个或多个数字，并且提供少于n个压缩电路，每个压缩电路适于（1）输入两个或多个数字; （2）关于用于定义n个间隔的范围的输入范围信息; 和（3）将两个以上的数字和范围信息压缩成两个以上的输出。该方法还包括采用少于n个压缩电路来确定n个间隔中的哪一个是两个或多个数字的和。提供了许多其他方面。

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