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81. 发明授权

US06420752B1 Semiconductor device with self-aligned contacts using a liner oxide layer 有权
标题翻译：具有使用衬垫氧化物层的自对准触点的半导体器件
公开(公告)号：US06420752B1
公开(公告)日：2002-07-16
申请号：US09502163
申请日：2000-02-11
申请人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
发明人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L21/76829 , H01L21/76897 , H01L27/115 , H01L2924/3011
摘要： A semiconductor device for minimizing auto-doping problems is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.
摘要翻译：公开了一种用于最小化自动掺杂问题的半导体器件。蚀刻停止层被消除并且被可消耗的衬垫氧化物层代替，使得该器件的层叠栅极结构可以被更靠近地放置在一起，从而允许器件收缩。衬垫氧化物层直接形成在衬底上并且与堆叠的栅极结构，侧壁间隔物以及形成在衬底上的源极和漏极接触并且用作介电层的自动掺杂势垒，以防止形成在衬底中的硼和磷电介质层自动掺入源和漏极。

82. 发明授权

US06417100B1 Annealing ambient in integrated circuit interconnects 失效
标题翻译：集成电路互连中的退火环境
公开(公告)号：US06417100B1
公开(公告)日：2002-07-09
申请号：US09874558
申请日：2001-06-04
申请人： Steven C. Avanzino , Pin-Chin Connie Wang , Minh Van Ngo
发明人： Steven C. Avanzino , Pin-Chin Connie Wang , Minh Van Ngo
IPC分类号： H01L214763
CPC分类号： H01L21/76877
摘要： A method of manufacturing an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer with an opening provided therein is formed on the semiconductor substrate. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. The integrated circuit is annealed in an atmosphere containing ammonia. This results in reduced hydrogen accumulation, improved bonding, and reduced electro-migration.
摘要翻译：提供一种具有半导体器件的半导体衬底的集成电路的制造方法。在半导体衬底上形成具有开口的器件介质层。屏障层对通道开口进行排列。导体芯填充阻挡层上的开口。集成电路在含有氨的气氛中退火。这导致减少的氢积聚，改善的结合和减少的电迁移。

83. 发明授权

US06383880B1 NH3/N2-plasma treatment for reduced nickel silicide bridging 有权
标题翻译： NH3 / N2等离子体处理用于还原硅化镍桥接
公开(公告)号：US06383880B1
公开(公告)日：2002-05-07
申请号：US09679374
申请日：2000-10-05
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Robert A. Huertas
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Robert A. Huertas
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518 , H01L21/3105
摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a plasma containing ammonia and nitrogen to create a clean surface region having increased nitrogen. Embodiments include treating the silicon nitride sidewall spacers with an ammonia and nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.
摘要翻译：通过用包含氨和氮的等离子体处理氮化硅侧壁间隔物的暴露表面以产生具有增加的氮的清洁表面区域来防止在栅电极上的硅化镍层和沿着氮化硅侧壁间隔物的源/漏区之间的桥接。实施例包括用氨和氮等离子体处理氮化硅侧壁间隔物以将表面区域的折射率降低到小于约1.95。

84. 发明授权

US06372673B1 Silicon-starved nitride spacer deposition 有权
标题翻译：缺硅氮化物间隔物沉积
公开(公告)号：US06372673B1
公开(公告)日：2002-04-16
申请号：US09781256
申请日：2001-02-13
申请人： Paul R. Besser , Minh Van Ngo , Christy Mei-Chu Woo , George Jonathan Kluth
发明人： Paul R. Besser , Minh Van Ngo , Christy Mei-Chu Woo , George Jonathan Kluth
IPC分类号： H01L21318
CPC分类号： H01L29/665 , H01L21/3185
摘要： Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming silicon-starved silicon nitride sidewall spacers having substantially no or significantly reduced Si available for reaction with deposited metal, e.g., nickel.
摘要翻译：通过形成具有基本上没有或显着减少的Si的硅绝缘氮化硅侧壁间隔物来避免金属硅化物（例如，硅化镍），栅极上的层和相关源极/漏极区域上的金属硅化物层之间的桥接，可用于与沉积金属反应，例如镍。

85. 发明授权

US06348732B1 Amorphized barrier layer for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的非晶化阻挡层
公开(公告)号：US06348732B1
公开(公告)日：2002-02-19
申请号：US09715702
申请日：2000-11-18
申请人： Sergey D. Lopatin , Minh Van Ngo , Minh Quoc Tran
发明人： Sergey D. Lopatin , Minh Van Ngo , Minh Quoc Tran
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/76862 , H01L21/76873 , H01L23/53209 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An amorphized barrier layer lines the opening and a seed layer is deposited to line the amorphized barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is securely bonded to the amorphized barrier layer and prevents electromigration along the surface between the seed and barrier layers.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。电介质层位于半导体衬底上，其中设有开口。非晶化的阻挡层对开口进行排列，并且沉积种子层以使非晶化的阻挡层排列。导体芯填充阻挡层上的开口以形成导体通道。种子层牢固地结合到非晶化阻挡层并防止沿种子和阻挡层之间的表面的电迁移。

86. 发明授权

US06333218B1 Method of etching contacts with reduced oxide stress 有权
标题翻译：蚀刻氧化应力减小接触的方法
公开(公告)号：US06333218B1
公开(公告)日：2001-12-25
申请号：US09501995
申请日：2000-02-11
申请人： Minh Van Ngo , Jayendra Bhakta , Paul Besser
发明人： Minh Van Ngo , Jayendra Bhakta , Paul Besser
IPC分类号： H01L218238
CPC分类号： H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/02337 , H01L21/31612 , H01L21/76224
摘要： A method for manufacturing a semiconductor device forms a trench of a trench isolation region in a portion of a top surface of a semiconductor substrates. Oxide is deposited as a trench liner in the trench using high temperature high density plasma (HDP) deposition. As the high temperature HDP oxide deposition is a stress neutral process, stress defects in an interface between the silicon substrate and the oxide layer are avoided, so that subsequent etching steps in a local interconnect process are less likely to overreach at the interface. This reduces the possibility of junction leakage when the local interconnect is formed.
摘要翻译：半导体器件的制造方法在半导体衬底的顶表面的一部分中形成沟槽隔离区的沟槽。使用高温高密度等离子体（HDP）沉积，氧化物作为沟槽衬垫沉积在沟槽中。由于高温HDP氧化物沉积是应力中性过程，因此避免了硅衬底和氧化物层之间的界面处的应力缺陷，使得局部互连工艺中的后续蚀刻步骤不太可能在界面处超范围。当局部互连形成时，这减少了结漏电的可能性。

87. 发明授权

US06225216B1 Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide 有权
标题翻译：形成具有改善的二氧化硅/硅化物蚀刻选择性的局部互连的方法
公开(公告)号：US06225216B1
公开(公告)日：2001-05-01
申请号：US09418490
申请日：1999-10-15
申请人： Minh Van Ngo , Yowjuang Bill Liu , Paul R. Besser
发明人： Minh Van Ngo , Yowjuang Bill Liu , Paul R. Besser
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/3185 , H01L21/76895
摘要： A method and arrangement for forming a local interconnect without weakening the field edge or disconnecting the diffusion region at the field edge provides an etch stop layer with increased density in comparison to conventionally deposited (e.g., plasma enhanced chemical vapor deposition (PECVD) etch stop layers. A low pressure chemical vapor deposition (LPCVD) process is used to deposit LPCVD SiN, using a high temperature in the deposition chamber. The increased temperature during deposition creates a highly dense, thermal SiN etch stop layer that is slower to etch than conventional PECVD SiON so that when etching the dielectric layer in which the local interconnect material is subsequently deposited, the etching stops at the etch stop layer in a controlled manner. This prevents the unintentional etching of the silicide region and diffusion region at the field edge.
摘要翻译：与常规沉积（例如，等离子体增强化学气相沉积（PECVD）蚀刻停止层（例如，等离子体增强化学气相沉积（PECVD））蚀刻停止层相比，用于形成局部互连而不削弱场边缘或在场边缘处断开扩散区域的方法和装置提供了具有增加的密度使用低压化学气相沉积（LPCVD）工艺来沉积LPCVD SiN，使用沉积室中的高温，沉积过程中增加的温度产生高度致密的热SiN蚀刻停止层，其比常规PECVD蚀刻更慢 SiON，使得当蚀刻其中随后沉积局部互连材料的电介质层时，蚀刻以受控的方式停止在蚀刻停止层处，这防止了在场边缘处的硅化物区域和扩散区域的无意蚀刻。

88. 发明授权

US06214731B1 Copper metalization with improved electromigration resistance 有权
标题翻译：铜金属化具有改善的电迁移率
公开(公告)号：US06214731B1
公开(公告)日：2001-04-10
申请号：US09442771
申请日：1999-11-18
申请人： Takeshi Nogami , Minh Van Ngo , Shekhar Pramanick
发明人： Takeshi Nogami , Minh Van Ngo , Shekhar Pramanick
IPC分类号： H01L2144
CPC分类号： H01L21/76856 , H01L21/76843 , H01L21/76855 , H01L21/76877 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Cu interconnection patterns with improved electromigration resistance are formed by depositing a barrier metal layer, such as W or WN, to line an opening in a dielectric layer. The exposed surface of the deposited barrier metal layer is treated with silane or dichlorosaline to form a thin silicon layer thereon. Cu is then deposited to fill the opening and reacted with the thin silicon layer to form a thin layer of Cu silicide at the interface between Cu and the barrier metal layer, thereby reducing the interface defect density and improving electromigration resistance.
摘要翻译：具有改善的电迁移电阻的Cu互连图案通过沉积阻挡金属层（例如W或WN）来形成，以对电介质层中的开口进行排列。沉积的阻挡金属层的暴露表面用硅烷或二氯苯胺处理以在其上形成薄硅层。然后沉积Cu以填充开口并与薄硅层反应以在Cu和阻挡金属层之间的界面处形成Cu硅化物的薄层，从而降低界面缺陷密度并提高电迁移阻力。

89. 发明授权

US06190966B1 Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration 失效
公开(公告)号：US06190966B1
公开(公告)日：2001-02-20
申请号：US08823953
申请日：1997-03-25
申请人： Minh Van Ngo , Sunil Mehta
发明人： Minh Van Ngo , Sunil Mehta
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/66825 , Y10S438/97
摘要： A semiconductor memory device such as a flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes a floating gate with high data retention. A tungsten damascene local interconnect structure includes a silicon nitride etch stop layer which is formed using Plasma Enhanced Chemical Vapor Deposition (PECVD) at a temperature of at least 480° C. such that the etch stop layer has a very low concentration of hydrogen ions. The minimization of hydrogen ions, which constitute mobile positive charge carriers, in the etch stop layer, minimizes recombination of the hydrogen ions with electrons on the floating gate, and thereby maximizes data retention of the device.

90. 发明授权

US6165894A Method of reliably capping copper interconnects 有权
标题翻译：铜互连可靠封盖的方法
公开(公告)号：US6165894A
公开(公告)日：2000-12-26
申请号：US131872
申请日：1998-08-10
申请人： Shekhar Pramanick , Takeshi Nogami , Minh Van Ngo
发明人： Shekhar Pramanick , Takeshi Nogami , Minh Van Ngo
IPC分类号： H01L21/768 , H01L23/532 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L21/76886 , H01L21/76834 , H01L21/76862 , H01L21/76877 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member with an ammonia plasma followed by depositing the diffusion barrier layer on the treated surface. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, treating the exposed surface of the Cu/Cu alloy interconnect with an ammonia plasma, and depositing a silicon nitride diffusion barrier layer directly on the plasma treated surface.
摘要翻译：通过用氨等离子体处理Cu或Cu合金互连构件的暴露表面，然后在经处理的表面上沉积扩散阻挡层，扩散阻挡层或覆盖层对Cu或Cu合金互连构件的粘附性显着增强。实施例包括电镀或化学镀Cu或Cu合金以填充介电中间层中的镶嵌开口，化学机械抛光，用氨等离子体处理Cu / Cu合金互连的暴露表面，并直接沉积氮化硅扩散阻挡层在等离子体处理的表面上。

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