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81. 发明授权

US06541866B1 Cobalt barrier for nickel silicidation of a gate electrode 有权
标题翻译：用于栅电极的镍硅化的钴屏障
公开(公告)号：US06541866B1
公开(公告)日：2003-04-01
申请号：US09778113
申请日：2001-02-07
申请人： Jacques J. Bertrand , Christy Mei-Chu Woo , Minh Van Ngo , George J. Kluth
发明人： Jacques J. Bertrand , Christy Mei-Chu Woo , Minh Van Ngo , George J. Kluth
IPC分类号： H01L2348
CPC分类号： H01L21/28052 , H01L29/4941
摘要： Nickel silicidation of a gate electrode is controlled using a cobalt barrier layer. Embodiments include forming a gate electrode structure comprising a lower polycrystalline silicon layer, a layer of cobalt thereon and an upper polycrystalline silicon layer on the cobalt layer, depositing a layer of nickel and silicidizing, whereby the upper polycrystalline silicon layer is converted to nickel suicide and a cobalt silicide barrier layer is formed preventing nickel from reacting with the lower polycrystalline silicon layer.
摘要翻译：使用钴阻挡层控制栅电极的镍硅化。实施例包括形成包括下多晶硅层，钴层上的钴层和钴层上的上多晶硅层的栅电极结构，沉积镍层和硅化物，由此将上多晶硅层转化为硅化镍，形成防止镍与下部多晶硅层反应的硅化钴阻挡层。

82. 发明授权

US06534869B2 Method for reducing stress-induced voids for 0.25 &mgr;m micron and smaller semiconductor chip technology by annealing interconnect lines prior to ILD deposition and semiconductor chip made thereby 失效
标题翻译：用于通过在ILD沉积之前退火互连线并由此制造的半导体芯片来减少0.25微米和更小的半导体芯片技术的应力诱导空隙的方法
公开(公告)号：US06534869B2
公开(公告)日：2003-03-18
申请号：US09128057
申请日：1998-07-29
申请人： Bryan Tracy , Paul R. Besser , Minh Van Ngo
发明人： Bryan Tracy , Paul R. Besser , Minh Van Ngo
IPC分类号： H01L2352
CPC分类号： H01L21/76858 , H01L21/76841 , H01L21/7685 , H01L21/76885 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms first, which subsequently volumetrically contracts, thereby forming a titanium aluminide compound, with the contraction being absorbed by the aluminum. Because the alloy is reacted to form the metal compound prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced.
摘要翻译：制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。在退火过程中，首先形成铝和钛的合金，其随后体积收缩，由此形成铝化铝化合物，其中收缩被铝吸收。因为在ILD沉积之前合金反应形成金属化合物，所以当它尝试吸收合金的收缩时，铝不受ILD的约束。因此，互连线中不希望的空隙形成的可能性降低。

83. 发明授权

US06479898B1 Dielectric treatment in integrated circuit interconnects 有权
标题翻译：集成电路互连中的介质处理
公开(公告)号：US06479898B1
公开(公告)日：2002-11-12
申请号：US09760421
申请日：2001-01-11
申请人： Dawn M. Hopper , Minh Van Ngo , Joffre F. Bernard
发明人： Dawn M. Hopper , Minh Van Ngo , Joffre F. Bernard
IPC分类号： H01L23532
CPC分类号： H01L21/76846 , H01L21/32051 , H01L21/76802 , H01L21/76826 , H01L21/76843 , H01L21/76855 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein and a surface region of nitrogen. A barrier layer lines the channel opening and reacts with the nitrogen to form an improved metal nitride surfaced barrier layer. A conductor core fills the opening over the barrier layer.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。形成在半导体衬底上的器件电介质层。器件电介质层上的沟道电介质层具有形成在其中的开口和氮的表面区域。阻挡层对通道开口进行排列并与氮反应以形成改进的金属氮化物表面的阻挡层。导体芯填充阻挡层上的开口。

84. 发明授权

US06462417B1 Coherent alloy diffusion barrier for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的相干合金扩散屏障
公开(公告)号：US06462417B1
公开(公告)日：2002-10-08
申请号：US09772750
申请日：2001-01-29
申请人： Pin-Chin Connie Wang , Amit P. Marathe , Minh Van Ngo , Suzette K. Pangrle
发明人： Pin-Chin Connie Wang , Amit P. Marathe , Minh Van Ngo , Suzette K. Pangrle
IPC分类号： H01L2348
CPC分类号： H01L21/76844 , H01L21/76843 , H01L21/76846 , H01L21/76855 , H01L21/76858 , H01L21/76873 , H01L21/76886 , H01L23/53209 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, an alloy-barrier layer lining the channel opening, and a conductor core filling the channel opening. An alloy layer is deposited which contains an element capable of reacting during thermal treatment with both the conductor core and the channel dielectric layer to form an alloy-barrier to diffusion of the material of the conductor core to the channel dielectric layer. The alloy-barrier layer is reacted with the conductor core and the channel dielectric layer to form a compound which provides a bond which blocks surface diffusion and permits conductor core to conductor core diffusion in dual inlaid integrated circuits.
摘要翻译：提供了一种集成电路及其制造方法，其具有半导体衬底，半导体器件和形成在半导体衬底上的器件电介质层。器件电介质层上的沟道电介质层具有通道开口，衬在沟道开口的合金阻挡层和填充沟道开口的导体芯。沉积合金层，其包含能够在热处理期间与导体芯和沟道介电层两者反应的元件，以形成对导体芯的材料扩散到沟道介电层的合金阻挡层。合金阻挡层与导体芯和沟道电介质层反应形成一种化合物，其提供阻挡表面扩散的键，并允许导体芯在双重嵌入式集成电路中的芯体扩散。

85. 发明授权

US06451647B1 Integrated plasma etch of gate and gate dielectric and low power plasma post gate etch removal of high-K residual 失效
标题翻译：栅极和栅极电介质的等离子体蚀刻和低功率等离子体栅极蚀刻去除高K残留的集成等离子体蚀刻
公开(公告)号：US06451647B1
公开(公告)日：2002-09-17
申请号：US10100819
申请日：2002-03-18
申请人： Chih-Yuh Yang , Minh Van Ngo
发明人： Chih-Yuh Yang , Minh Van Ngo
IPC分类号： H01L218242
CPC分类号： H01L21/28194 , H01L21/2807 , H01L21/28123 , H01L21/28273 , H01L21/28282 , H01L21/28291 , H01L21/31116 , H01L21/32137 , H01L21/32139 , H01L29/517
摘要： The present invention relates to a process of fabricating a semiconductor device, including steps of providing a first semiconductor wafer; depositing on the first semiconductor wafer a layer comprising a high-K dielectric material layer; depositing on the layer comprising a high-K dielectric material a polysilicon or polysilicon-germanium layer; and forming a gate stack by plasma etching both a portion of the polysilicon or polysilicon-germanium layer and a portion of the layer comprising a high-K dielectric material in a single chamber. In one embodiment, the step of plasma etching is carried out without moving the first wafer from the chamber. In another embodiment an unwanted residual high-K dielectric material is removed by applying a low power plasma treatment.
摘要翻译：本发明涉及制造半导体器件的方法，包括提供第一半导体晶片的步骤; 在第一半导体晶片上沉积包含高K电介质材料层的层; 在包括高K电介质材料的层上沉积多晶硅或多晶硅 - 锗层; 以及通过在单个室中等离子体蚀刻多晶硅或多晶硅 - 锗层的一部分和包含高K电介质材料的层的一部分来形成栅叠层。在一个实施例中，在不从腔室移动第一晶片的情况下执行等离子体蚀刻的步骤。在另一个实施例中，通过施加低功率等离子体处理来去除不想要的残余高K电介质材料。

86. 发明授权

US06445070B1 Coherent carbide diffusion barrier for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的相干碳化物扩散屏障
公开(公告)号：US06445070B1
公开(公告)日：2002-09-03
申请号：US09772715
申请日：2001-01-29
申请人： Pin-Chin Connie Wang , Amit P. Marathe , Minh Van Ngo , Suzette K. Prangrle
发明人： Pin-Chin Connie Wang , Amit P. Marathe , Minh Van Ngo , Suzette K. Prangrle
IPC分类号： H01L2348
CPC分类号： H01L23/53223 , H01L23/5226 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefore is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, a barrier layer lining the channel opening, and a conductor core filling the channel opening. A barrier layer is deposited which contains an element capable of reacting during thermal treatment with both the conductor core and the channel dielectric layer to form a barrier to diffusion of the material of the conductor core to the channel dielectric layer. The barrier layer reacts with the conductor core and the channel dielectric layer to form a compound which provides a bond which blocks surface diffusion and permits conductor core to conductor core diffusion in dual inlaid integrated circuits.
摘要翻译：因此，提供了具有半导体器件的半导体衬底和形成在半导体衬底上的器件电介质层的集成电路和制造方法。器件电介质层上的沟道电介质层具有通道开口，衬在通道开口的阻挡层和填充通道开口的导体芯。沉积阻挡层，其包含能够在热处理期间与导体芯和沟道介电层两者反应的元件，以形成导体芯材料扩散到沟道介电层的障碍。阻挡层与导体芯和沟道介电层反应形成一种化合物，其提供阻挡表面扩散的键，并允许导体芯与双重镶嵌集成电路中的导体芯扩散。

87. 发明授权

US06441490B1 Low dielectric constant stop layer for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的低介电常数阻挡层
公开(公告)号：US06441490B1
公开(公告)日：2002-08-27
申请号：US09774849
申请日：2001-01-30
申请人： Minh Van Ngo , Christy Mei-Chu Woo
发明人： Minh Van Ngo , Christy Mei-Chu Woo
IPC分类号： H01L2940
CPC分类号： H01L23/5329 , H01L21/76807 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening and a conductor core filling the channel opening. A via stop layer is formed over the channel dielectric layer to have a hydrogen concentration below 15 atomic % and a via dielectric layer is formed over the via stop layer and has a via opening. A second channel dielectric layer over the via dielectric layer has a second channel opening. A second conductor core, filling the second channel opening and the via opening, is connected to the semiconductor device.
摘要翻译：提供了一种集成电路及其制造方法，其具有半导体衬底，半导体器件和形成在半导体衬底上的器件电介质层。器件电介质层上的沟道电介质层具有通道开口和填充沟道开口的导体芯。在通道电介质层上形成通孔停止层，使氢浓度低于15原子％，并且在通孔停止层上方形成通孔电介质层，并具有通孔。通孔电介质层上的第二通道介电层具有第二通道开口。填充第二通道开口和通孔开口的第二导体芯连接到半导体器件。

88. 发明授权

US06420752B1 Semiconductor device with self-aligned contacts using a liner oxide layer 有权
标题翻译：具有使用衬垫氧化物层的自对准触点的半导体器件
公开(公告)号：US06420752B1
公开(公告)日：2002-07-16
申请号：US09502163
申请日：2000-02-11
申请人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
发明人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L21/76829 , H01L21/76897 , H01L27/115 , H01L2924/3011
摘要： A semiconductor device for minimizing auto-doping problems is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.
摘要翻译：公开了一种用于最小化自动掺杂问题的半导体器件。蚀刻停止层被消除并且被可消耗的衬垫氧化物层代替，使得该器件的层叠栅极结构可以被更靠近地放置在一起，从而允许器件收缩。衬垫氧化物层直接形成在衬底上并且与堆叠的栅极结构，侧壁间隔物以及形成在衬底上的源极和漏极接触并且用作介电层的自动掺杂势垒，以防止形成在衬底中的硼和磷电介质层自动掺入源和漏极。

89. 发明授权

US06417100B1 Annealing ambient in integrated circuit interconnects 失效
标题翻译：集成电路互连中的退火环境
公开(公告)号：US06417100B1
公开(公告)日：2002-07-09
申请号：US09874558
申请日：2001-06-04
申请人： Steven C. Avanzino , Pin-Chin Connie Wang , Minh Van Ngo
发明人： Steven C. Avanzino , Pin-Chin Connie Wang , Minh Van Ngo
IPC分类号： H01L214763
CPC分类号： H01L21/76877
摘要： A method of manufacturing an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer with an opening provided therein is formed on the semiconductor substrate. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. The integrated circuit is annealed in an atmosphere containing ammonia. This results in reduced hydrogen accumulation, improved bonding, and reduced electro-migration.
摘要翻译：提供一种具有半导体器件的半导体衬底的集成电路的制造方法。在半导体衬底上形成具有开口的器件介质层。屏障层对通道开口进行排列。导体芯填充阻挡层上的开口。集成电路在含有氨的气氛中退火。这导致减少的氢积聚，改善的结合和减少的电迁移。

90. 发明授权

US06383880B1 NH3/N2-plasma treatment for reduced nickel silicide bridging 有权
标题翻译： NH3 / N2等离子体处理用于还原硅化镍桥接
公开(公告)号：US06383880B1
公开(公告)日：2002-05-07
申请号：US09679374
申请日：2000-10-05
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Robert A. Huertas
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Robert A. Huertas
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518 , H01L21/3105
摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a plasma containing ammonia and nitrogen to create a clean surface region having increased nitrogen. Embodiments include treating the silicon nitride sidewall spacers with an ammonia and nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.
摘要翻译：通过用包含氨和氮的等离子体处理氮化硅侧壁间隔物的暴露表面以产生具有增加的氮的清洁表面区域来防止在栅电极上的硅化镍层和沿着氮化硅侧壁间隔物的源/漏区之间的桥接。实施例包括用氨和氮等离子体处理氮化硅侧壁间隔物以将表面区域的折射率降低到小于约1.95。

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