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81. 发明授权

US08365697B2 Internal combustion engine 有权
公开(公告)号：US08365697B2
公开(公告)日：2013-02-05
申请号：US12478622
申请日：2009-06-04
申请人： James M. Cleeves
发明人： James M. Cleeves
IPC分类号： F01L5/04
CPC分类号： F02F1/14 , F01L5/06 , F01L7/00 , F01L7/04 , F01L9/02 , F01L2820/033 , F01P2003/021 , F02B25/08 , F02B75/28 , F02B75/282 , F02D13/0269 , F02D13/028 , F02D15/02 , F02F1/186 , Y02T10/142
摘要： An internal combustion engine is provided. Facing pistons eliminate a cylinder head, thereby reducing heat losses through a cylinder head. Facing pistons also halve the stroke that would be required for one piston to provide the same compression ratio, and the engine can thus be run at higher revolutions per minute and produce more power. An internal sleeve valve is provided for space and other considerations. A combustion chamber size-varying mechanism allows for adjustment of the minimum size of an internal volume to increase efficiency at partial-power operation. Variable intake valve operation is used to control engine power.

82. 发明申请

US20130009230A1 OPTIMIZATION OF CRITICAL DIMENSIONS AND PITCH OF PATTERNED FEATURES IN AND ABOVE A SUBSTRATE 有权
标题翻译：关键尺寸的优化和基板上及以上图案特征的优化
公开(公告)号：US20130009230A1
公开(公告)日：2013-01-10
申请号：US13613956
申请日：2012-09-13
申请人： James M. Cleeves , Roy E. Scheuerlein
发明人： James M. Cleeves , Roy E. Scheuerlein
IPC分类号： H01L27/088 , H01L27/02
CPC分类号： H01L27/105 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.
摘要翻译：在使用光刻和蚀刻技术的不同器件级别和那些器件级别的区域中，使用不同且优化的临界尺寸形成管芯。本发明的一个方面提供了形成在衬底上的存储器阵列，其中驱动电路形成在衬底中。存储器阵列的一个级别包括例如平行轨道和扇出区域。希望使轨道的密度最大化并最小化整个存储器阵列的光刻成本。这可以通过以比它下面的CMOS电路更紧的间距形成轨道来实现，从而允许在形成CMOS时使用更便宜的光刻工具，并且类似地通过优化用于器件级别的光刻和蚀刻技术以在轨道，并且在不太关键的扇出区域更放松。

83. 发明申请

US20120085305A1 POSITIVE CONTROL (DESMODROMIC) VALVE SYSTEMS FOR INTERNAL COMBUSTION ENGINES 有权
标题翻译：用于内燃机的积极控制（DESMODROMIC）阀系统
公开(公告)号：US20120085305A1
公开(公告)日：2012-04-12
申请号：US13269539
申请日：2011-10-07
申请人： James M. Cleeves , Michael Hawkes , William H. Anderson
发明人： James M. Cleeves , Michael Hawkes , William H. Anderson
IPC分类号： F01L5/08 , F01L1/30
CPC分类号： F01L1/30 , F01L1/08 , F01L1/181 , F01L1/22 , F01L1/2405 , F01L5/06 , F01L7/04 , F01L2001/186 , F02B75/282
摘要： Various types of valve systems are disclosed herein. In one embodiment, a positive control reciprocating sleeve valve system for use with an internal combustion engine includes opening and closing rockers controlled by corresponding opening and closing cam lobes. In one aspect of this embodiment, interference can be designed into the valve control system to provide additional “hold-closed” force to hold the valve against its seat during a portion of the engine cycle. In another aspect of this embodiment, positive control valve systems can include compliant components and systems, hydraulic systems, pneumatic systems, and/or mechanical spring systems to control valve lash, facilitate sealing, etc.
摘要翻译：本文公开了各种类型的阀系统。在一个实施例中，与内燃机一起使用的正控制往复式套筒阀系统包括由对应的打开和关闭凸轮凸角控制的打开和关闭摇杆。在该实施例的一个方面，可以将干扰设计到阀控制系统中以在发动机循环的一部分期间提供额外的“保持关闭”力以将阀保持在其阀座上。在该实施例的另一方面，积极的控制阀系统可以包括顺应部件和系统，液压系统，气动系统和/或机械弹簧系统，以控制阀间隙，便于密封等。

84. 发明授权

US07978492B2 Integrated circuit incorporating decoders disposed beneath memory arrays 有权
标题翻译：集成电路，包含设置在存储器阵列下方的解码器
公开(公告)号：US07978492B2
公开(公告)日：2011-07-12
申请号：US12725269
申请日：2010-03-16
申请人： Mark G. Johnson , Thomas H. Lee , James M. Cleeves
发明人： Mark G. Johnson , Thomas H. Lee , James M. Cleeves
IPC分类号： G11C5/06
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要翻译：公开了一种非常高密度的现场可编程存储器。阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。自动对准技术的最大限度地使光刻限制最小化。在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。

85. 发明申请

US20100212622A1 SLEEVE VALVE ASSEMBLY 失效
标题翻译：套筒阀组件
公开(公告)号：US20100212622A1
公开(公告)日：2010-08-26
申请号：US12710248
申请日：2010-02-22
申请人： James M. Cleeves
发明人： James M. Cleeves
IPC分类号： F01L5/04 , F16K49/00 , F01L7/02
CPC分类号： F01L5/06 , F01L7/04 , Y10T137/6416
摘要： A sleeve valve assembly. The assembly includes a valve seat, a sleeve valve and an oil path-defining piece. The sleeve valve includes a distal end with a cavity. The distal end contacts the valve seat when the sleeve valve is located in a closed position. The oil path-defining piece includes an inlet port, an outlet port and a plurality of cooling passages. The flange of the sleeve valve is slidably in contact with the oil path-defining piece such that cooling fluid travelling into the inlet port and through the cooling passages enters into the cavity before exiting out the exit port.
摘要翻译：套筒阀组件。组件包括阀座，套筒阀和油路限定件。套筒阀包括具有空腔的远端。当套筒阀位于关闭位置时，远端与阀座接触。油路限定件包括入口端口，出口端口和多个冷却通道。套筒阀的凸缘与油路限定件可滑动地接触，使得流入入口和冷却通道的冷却流体在离开出口之前进入空腔。

86. 发明申请

US20100171152A1 INTEGRATED CIRCUIT INCORPORATING DECODERS DISPOSED BENEATH MEMORY ARRAYS 有权
标题翻译：集成电路整合解码器处理BENEATH存储器阵列
公开(公告)号：US20100171152A1
公开(公告)日：2010-07-08
申请号：US12725269
申请日：2010-03-16
申请人： Mark G. Johnson , Thomas H. Lee , James M. Cleeves
发明人： Mark G. Johnson , Thomas H. Lee , James M. Cleeves
IPC分类号： H01L27/10
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要翻译：公开了一种非常高密度的现场可编程存储器。阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。自动对准技术的最大限度地使光刻限制最小化。在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。

87. 发明申请

US20080119027A1 VERTICALLY STACKED FIELD PROGRAMMABLE NONVOLATILE MEMORY AND METHOD OF FABRICATION 有权
标题翻译：垂直堆叠现场可编程非易失性存储器和制造方法
公开(公告)号：US20080119027A1
公开(公告)日：2008-05-22
申请号：US11925723
申请日：2007-10-26
申请人： Vivek Subramanian , James M. Cleeves
发明人： Vivek Subramanian , James M. Cleeves
IPC分类号： H01L21/822
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要翻译：公开了一种非常高密度的现场可编程存储器。阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。自动对准技术的最大限度地使光刻限制最小化。在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。

88. 发明授权

US07309951B2 Spark plug 有权
标题翻译：火花塞
公开(公告)号：US07309951B2
公开(公告)日：2007-12-18
申请号：US11444935
申请日：2006-05-31
申请人： James M. Cleeves
发明人： James M. Cleeves
IPC分类号： H01T13/46
CPC分类号： H01T13/467 , H01T13/462 , H01T13/50
摘要： A spark plug is disclosed having at least one main electrode and at least one secondary electrode. The gaps associated with the secondary electrodes are between one third and two thirds the optimum gap distance. Resistors associated with the secondary electrodes control the current flow and therefore the voltage on the electrodes.
摘要翻译：公开了具有至少一个主电极和至少一个次级电极的火花塞。与次级电极相关的间隙是最佳间隙距离的三分之一和三分之二。与次级电极相关联的电阻器控制电流，因此控制电极上的电压。

89. 发明授权

US07157314B2 Vertically stacked field programmable nonvolatile memory and method of fabrication 有权
公开(公告)号：US07157314B2
公开(公告)日：2007-01-02
申请号：US09939498
申请日：2001-08-24
申请人： Vivek Subramanian , James M. Cleeves
发明人： Vivek Subramanian , James M. Cleeves
IPC分类号： H01L21/82
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

90. 发明授权

US06677204B2 Multigate semiconductor device with vertical channel current and method of fabrication 失效
标题翻译：具有垂直沟道电流的半导体器件和制造方法
公开(公告)号：US06677204B2
公开(公告)日：2004-01-13
申请号：US10254878
申请日：2002-09-26
申请人： James M. Cleeves , Vivek Subramanian
发明人： James M. Cleeves , Vivek Subramanian
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , G11C11/5621 , G11C11/5671 , G11C16/0458 , G11C16/0475 , G11C2211/5611 , G11C2211/5612 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11556 , H01L29/66825 , H01L29/66833 , H01L29/7881
摘要： The present invention is a multibit nonvolatile memory and its method of fabrication. According to the present invention a silicon channel body having a first and second channel surface is formed. A charge storage medium is formed adjacent to the first channel surface and a second charge storage medium is formed adjacent to the second channel surface. A first control gate is formed adjacent to the first charge storage medium adjacent to the first channel surface and a second control gate is formed adjacent to the second charge storage medium adjacent to the second surface.
摘要翻译：本发明是一种多位非易失性存储器及其制造方法。根据本发明，形成具有第一和第二通道表面的硅通道体。在第一通道表面附近形成电荷存储介质，并且在第二通道表面附近形成第二电荷存储介质。与第一通道表面相邻的第一电荷存储介质相邻地形成第一控制栅极，并且邻近第二表面邻近第二电荷存储介质形成第二控制栅极。

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