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81. 发明授权

US08258576B2 Method of manufacturing a semiconductor device including epitaxially growing semiconductor epitaxial layers on a surface of semiconductor substrate 有权
标题翻译：在半导体衬底的表面上制造包括外延生长半导体外延层的半导体器件的方法
公开(公告)号：US08258576B2
公开(公告)日：2012-09-04
申请号：US12541279
申请日：2009-08-14
申请人： Hiroyuki Ohta
发明人： Hiroyuki Ohta
IPC分类号： H01L27/12
CPC分类号： H01L21/823814 , H01L21/823418 , H01L21/823807 , H01L27/092 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device has a first MOS transistor formed on first active region of the first conductivity type, having first gate electrode structure, first source/drain regions, recesses formed in the first source/drain regions, and semiconductor buried regions buried and grown on the recesses for applying stress to the channel under the first gate electrode structure, and a second MOS transistor formed on second active region of the second conductivity type, having second gate electrode structure, second source/drain regions, and semiconductor epitaxial layers formed on the second source/drain regions without forming recesses and preferably applying stress to the channel under the second gate electrode structure. In a CMOS device, performance can be improved by utilizing stress and manufacture processes can be simplified.
摘要翻译：半导体器件具有形成在第一导电类型的第一有源区上的第一MOS晶体管，具有第一栅极电极结构，第一源极/漏极区域，形成在第一源极/漏极区域中的凹槽，以及在用于对第一栅电极结构下的沟道施加应力的凹部和形成在第二导电类型的第二有源区上的第二MOS晶体管，具有形成在第二栅电极结构上的第二栅电极结构，第二源/漏区和半导体外延层源极/漏极区，而不形成凹槽，并且优选地在第二栅电极结构下的沟道处施加应力。在CMOS器件中，可以通过利用应力来提高性能，并且可以简化制造工艺。

82. 发明授权

US08207042B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US08207042B2
公开(公告)日：2012-06-26
申请号：US12564313
申请日：2009-09-22
申请人： Yosuke Shimamune , Masahiro Fukuda , Young Suk Kim , Akira Katakami , Akiyoshi Hatada , Naoyoshi Tamura , Hiroyuki Ohta
发明人： Yosuke Shimamune , Masahiro Fukuda , Young Suk Kim , Akira Katakami , Akiyoshi Hatada , Naoyoshi Tamura , Hiroyuki Ohta
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.

83. 发明授权

US08164085B2 Semiconductor device and production method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08164085B2
公开(公告)日：2012-04-24
申请号：US12916953
申请日：2010-11-01
申请人： Yosuke Shimamune , Hiroyuki Ohta , Akiyoshi Hatada , Akira Katakami , Naoyoshi Tamura
发明人： Yosuke Shimamune , Hiroyuki Ohta , Akiyoshi Hatada , Akira Katakami , Naoyoshi Tamura
IPC分类号： H01L29/06
CPC分类号： H01L29/165 , H01L29/045 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.
摘要翻译：公开了一种制造半导体器件的方法，其能够抑制短沟道效应并改善载流子迁移率。在该方法中，在对应于源极区和漏极区的硅衬底中形成沟槽。当外延生长p型半导体混晶层以填充沟槽时，沟槽的表面被刻面划分，半导体混晶层的延伸部分形成在第二侧壁绝缘膜的底表面和硅衬底和延伸部分与源极延伸区域和漏极延伸区域接触。

84. 发明授权

US08146443B2 Rotating body dynamic quantity measuring device and system 有权
标题翻译：旋转体动力测量装置及系统
公开(公告)号：US08146443B2
公开(公告)日：2012-04-03
申请号：US12761970
申请日：2010-04-16
申请人： Hiroyuki Ohta , Takashi Sumigawa
发明人： Hiroyuki Ohta , Takashi Sumigawa
IPC分类号： G01L1/22
CPC分类号： G01L3/108 , G01L1/18 , G01L1/2293 , G01L3/10
摘要： A single crystal semiconductor including a Wheatstone bridge circuit formed of an impurity diffusion layer whose longitudinal direction is aligned with a particular crystal orientation is connected to a rotating body. A rotating body dynamic quantity measuring device and a system using the measuring device are fatigue- and corrosion-resistant because of the single crystal semiconductor used and are not easily affected by temperature variations because of the bridge circuit considering a single crystal anisotropy.
摘要翻译：包括由纵向与特定晶体取向对准的杂质扩散层形成的惠斯通电桥电路的单晶半导体连接到旋转体。旋转体动量测量装置和使用该测量装置的系统由于使用单晶半导体而具有耐疲劳和耐腐蚀性，并且由于考虑到单晶各向异性的桥式电路，不容易受到温度变化的影响。

85. 发明授权

US07992448B2 Mechanical-quantity measuring device 有权
标题翻译：机械量测量装置
公开(公告)号：US07992448B2
公开(公告)日：2011-08-09
申请号：US11709075
申请日：2007-02-20
申请人： Hiromi Shimazu , Hiroyuki Ohta , Yohei Tanno
发明人： Hiromi Shimazu , Hiroyuki Ohta , Yohei Tanno
IPC分类号： G01L1/18 , G01L1/22
CPC分类号： G01L1/2293 , G01B7/18 , G01L1/18
摘要： A mechanical-quantity measuring device capable of measuring a strain component in a specific direction with high precision is provided.At least two or more pairs of bridge circuits are formed inside a semiconductor monocrystal substrate and a semiconductor chip, and one of these bridge circuits forms a n-type diffusion resistor in which a direction of a current flow and measuring variation of a resistor value are in parallel with a direction of the semiconductor monocrystal silicon substrate, and an another bridge circuit is composed of combination of p-type diffusion resistors in parallel with a direction.
摘要翻译：提供能够高精度地测量特定方向的应变分量的机械量测量装置。在半导体单晶基板和半导体芯片的内部形成有至少两对以上的桥式电路，并且这些桥式电路之一形成n型扩散电阻器，其中电流方向和电阻值的测量变化为与半导体单晶硅衬底的<100>方向并联，并且另一桥接电路由与<110>方向平行的p型扩散电阻器的组合组成。

86. 发明授权

US07977194B2 Method for fabricating semiconductor device with fully silicided gate electrode 有权
标题翻译：制造具有全硅化物栅电极的半导体器件的方法
公开(公告)号：US07977194B2
公开(公告)日：2011-07-12
申请号：US11492199
申请日：2006-07-25
申请人： Hidenobu Fukutome , Hiroyuki Ohta , Kazuo Kawamura , Kimihiko Hosaka
发明人： Hidenobu Fukutome , Hiroyuki Ohta , Kazuo Kawamura , Kimihiko Hosaka
IPC分类号： H01L21/8234
CPC分类号： H01L21/823443 , H01L21/28097 , H01L21/823456 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method for fabricating a semiconductor device includes the steps of: forming a first MISFET including first source/drain regions and a first gate electrode of a polycrystalline silicon, and a second MISFET including second source/drain regions and a second gate electrode of a polycrystalline silicon and having a gate length larger than that of the first gate electrode; and substituting the polycrystalline silicon forming the first and the second gate electrodes with a metal silicide. In the step of substituting the polycrystalline silicon with the metal silicide, the polycrystalline silicon forming the first gate electrode is totally substituted with the metal silicide and a part of polycrystalline silicon forming the second gate electrode is substituted with the metal silicide by utilizing that the gate length of the second gate electrode is larger than the gate length of the first gate electrode.
摘要翻译：一种制造半导体器件的方法包括以下步骤：形成第一MISFET，其包括多晶硅的第一源极/漏极区域和第一栅极电极，以及包括第二源极/漏极区域和第二栅极电极的第二MISFET，硅，其栅极长度大于第一栅电极的栅极长度; 以及用金属硅化物代替形成第一和第二栅电极的多晶硅。在用金属硅化物代替多晶硅的步骤中，形成第一栅电极的多晶硅完全被金属硅化物置换，并且形成第二栅极的部分多晶硅被金属硅化物取代，利用栅极第二栅电极的长度大于第一栅电极的栅极长度。

87. 发明授权

US07836755B2 Solidification sensor 有权
标题翻译：凝固传感器
公开(公告)号：US07836755B2
公开(公告)日：2010-11-23
申请号：US11943753
申请日：2007-11-21
申请人： Hiromi Shimazu , Hiroyuki Ohta , Yohei Tanno , Mari Uchida , Naoto Saito
发明人： Hiromi Shimazu , Hiroyuki Ohta , Yohei Tanno , Mari Uchida , Naoto Saito
IPC分类号： G01N33/00 , G01N37/00 , G01N33/18 , G01N33/487
CPC分类号： G01N25/02 , G01N2203/0075 , G01N2203/0092
摘要： In a solidification sensor for measuring a solidification state of a liquid with a high degree of accuracy in real time, and for making the sensor small-sized with a reduced power consumption, the solidification sensor comprises a liquid absorbing portion formed of a liquid absorbable material, a substrate coupled to the liquid absorbing portion and a strain sensor for measuring strain exerted to the substrate due to a volumetric change upon solidification of a liquid absorbed in the liquid absorbing portion.
摘要翻译：在用于以实时高精度测量液体的凝固状态的凝固传感器中，并且为了使传感器小型化而具有降低的功率消耗，凝固传感器包括由液体吸收材料形成的液体吸收部分，耦合到液体吸收部分的基板和用于测量由于吸收在液体吸收部分中的液体固化时的体积变化而测量施加到基板的应变传感器。

88. 发明申请

US20090321783A1 Semiconductor Device 失效
标题翻译：半导体器件
公开(公告)号：US20090321783A1
公开(公告)日：2009-12-31
申请号：US12493502
申请日：2009-06-29
申请人： Shinji Hiramitsu , Hiroyuki Ohta , Koji Sasaki , Masato Nakamura , Osamu Ikeda , Satoshi Matsuyoshi
发明人： Shinji Hiramitsu , Hiroyuki Ohta , Koji Sasaki , Masato Nakamura , Osamu Ikeda , Satoshi Matsuyoshi
IPC分类号： H01L29/86
CPC分类号： H01L23/051 , H01L23/24 , H01L2224/33181
摘要： A semiconductor device which includes a semiconductor chip; an electrically conductive base electrode bonded to the lower surface of the semiconductor chip by a first bonding member; an electrically conductive lead electrode bonded to the upper surface of the semiconductor chip by a second bonding member; and a first stress relief member for reducing stress developed in the first bonding member due to the difference in thermal expansion between the semiconductor chip and the base electrode, wherein both the base electrode and the first stress relief member are in direct contact with the lower surface of the first bonding member.
摘要翻译：一种半导体器件，包括半导体芯片; 通过第一接合部件接合到半导体芯片的下表面的导电基极; 导电引线电极，通过第二接合构件接合到半导体芯片的上表面; 以及由于所述半导体芯片和所述基极之间的热膨胀差异而减小在所述第一接合构件中产生的应力的第一应力消除构件，其中所述基极和所述第一应力消除构件都与所述下表面直接接触的第一粘合构件。

89. 发明授权

US07626215B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07626215B2
公开(公告)日：2009-12-01
申请号：US11604694
申请日：2006-11-28
申请人： Yosuke Shimamune , Masahiro Fukuda , Young Suk Kim , Akira Katakami , Akiyoshi Hatada , Naoyoshi Tamura , Hiroyuki Ohta
发明人： Yosuke Shimamune , Masahiro Fukuda , Young Suk Kim , Akira Katakami , Akiyoshi Hatada , Naoyoshi Tamura , Hiroyuki Ohta
IPC分类号： H01L29/78
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.
摘要翻译：在沟槽中通过外延生长法形成第一p型SiGe混晶层，形成第二p型SiGe混晶层。在第二SiGe混晶层上形成第三p型SiGe混晶层。从沟槽底部开始的第一SiGe混合晶体层的最上表面的高度低于沟槽的深度，硅衬底的表面是标准的。从沟槽底部开始的第二SiGe混合晶体层的最上表面的高度高于沟槽的深度，硅衬底的表面是标准的。第一和第三SiGe混晶层中的Ge浓度低于第二SiGe混晶层中的Ge浓度。

90. 发明授权

US07589391B2 Semiconductor device with STI and its manufacture 有权
标题翻译：具有STI的半导体器件及其制造
公开(公告)号：US07589391B2
公开(公告)日：2009-09-15
申请号：US11433671
申请日：2006-05-15
申请人： Hiroyuki Ohta , Yasunori Iriyama
发明人： Hiroyuki Ohta , Yasunori Iriyama
IPC分类号： H01L21/762
CPC分类号： H01L21/823481 , H01L21/76224
摘要： A semiconductor device includes: a silicon substrate with semiconductor elements; an isolation trench formed in the silicon substrate for isolating active regions in the silicon substrate, the isolation trench having a trapezoidal cross sectional shape having a width gradually narrowing with a depth from the surface of the silicon substrate; a first liner insulating film formed on the surface of the trench and made of a silicon oxide film or a silicon oxynitride film having a thickness of 1 to 5 nm; a second liner insulating film formed on the first liner insulating film and made of a silicon nitride film having a thickness of 2 to 8 nm; and an isolation region burying the trench defined by the second liner insulating film.
摘要翻译：半导体器件包括：具有半导体元件的硅衬底; 在所述硅衬底中形成的用于隔离所述硅衬底中的有源区的隔离沟槽，所述隔离沟槽具有梯形截面形状，所述梯形横截面形状具有从所述硅衬底的表面的深度逐渐变窄的宽度; 第一衬垫绝缘膜，形成在沟槽的表面上，由厚度为1至5nm的氧化硅膜或氮氧化硅膜制成; 形成在第一衬垫绝缘膜上并由厚度为2至8nm的氮化硅膜制成的第二衬垫绝缘膜; 以及掩埋由第二衬垫绝缘膜限定的沟槽的隔离区域。

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