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81. 发明申请

US20080185649A1 Substrate backgate for trigate FET 有权
标题翻译：基板背板用于触发FET
公开(公告)号：US20080185649A1
公开(公告)日：2008-08-07
申请号：US12099211
申请日：2008-04-08
申请人： Brent A. Anderson , Matthew J. Breitwisch , Edward J. Nowak
发明人： Brent A. Anderson , Matthew J. Breitwisch , Edward J. Nowak
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back gate can be used to control the threshold voltage of the FET. In one embodiment the back gate extends to an n-well in a p-type silicon substrate. A contact to the n-well allows electrical voltage to be applied to the back gate. A diode created between the n-well and p-substrate isolates the current flowing through the n-well from other devices on the substrate so that the back gate can be independently biased. In another embodiment the back gate extends to n-type polysilicon layer on an insulator layer on a p-type silicon substrate. A contact to the n-type polysilicon layer allows electrical voltage to be applied to the back gate. A trench isolation structure extending through the polysilicon layer to the insulator layer isolates current flowing through the polysilicon layer from other devices on the silicon substrate.
摘要翻译：公开了具有背栅的三栅场效应晶体管和形成晶体管的相关方法。具体地说，后门结合在翅片的下部。三栅结构形成在翅片上并与后门电隔离。背栅可用于控制FET的阈值电压。在一个实施例中，背栅极延伸到p型硅衬底中的n阱。与n阱的接触允许将电压施加到后门。在n阱和p衬底之间产生的二极管将流过n阱的电流与衬底上的其他器件隔离，使得后栅极可以被独立地偏置。在另一个实施例中，背栅极延伸到p型硅衬底上的绝缘体层上的n型多晶硅层。与n型多晶硅层的接触允许电压施加到后门。通过多晶硅层延伸到绝缘体层的沟槽隔离结构将流过多晶硅层的电流与硅衬底上的其它器件隔离。

82. 发明授权

US06700163B2 Selective silicide blocking 有权
标题翻译：选择性硅化物封闭
公开(公告)号：US06700163B2
公开(公告)日：2004-03-02
申请号：US09683278
申请日：2001-12-07
申请人： Matthew J. Breitwisch , Jeffrey S. Brown , Terence B. Hook , Randy W. Mann , Christopher S. Putnam , Mohammad I. Younus
发明人： Matthew J. Breitwisch , Jeffrey S. Brown , Terence B. Hook , Randy W. Mann , Christopher S. Putnam , Mohammad I. Younus
IPC分类号： H01L2976
CPC分类号： H01L21/823871 , H01L21/823842
摘要： A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has suicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area at the N+/P+ junction of the polysilicon line, and silicide is not present on the N+ active area and the P+ active area. The presence of this selective silicidation creates a beneficial low-resistance connection between the N+ region of the polysilicon line and the P+ region of the polysilicon line. The absence of silicidation on the N+ and P+ active areas, specifically on the PFET and NFET structures, prevents current leakage associated with the silicidation of devices.
摘要翻译：本文公开了选择性硅化半导体结构及其制造方法。半导体结构在N +扩散或N +有源区域之间的多晶硅线路上存在自杀，并且在多晶硅线路的N + / P +结处的P +扩散或有源区域存在自杀，并且在N +有源区域和P +活性区域上不存在硅化物区。这种选择性硅化的存在在多晶硅线的N +区和多晶硅线的P +区之间产生有益的低电阻连接。在N +和P +有源区，特别是PFET和NFET结构上不存在硅化，可防止与器件硅化相关的电流泄漏。

83. 发明授权

US06667205B2 Method of forming retrograde n-well and p-well 失效
标题翻译：逆行n井和p井的形成方法
公开(公告)号：US06667205B2
公开(公告)日：2003-12-23
申请号：US10063406
申请日：2002-04-19
申请人： Matthew J. Breitwisch , Chung H. Lam , James A. Slinkman
发明人： Matthew J. Breitwisch , Chung H. Lam , James A. Slinkman
IPC分类号： H01L218238
CPC分类号： H01L21/823878 , H01L21/823892
摘要： A method of forming retrograde n-wells and p-wells. A first mask is formed on the substrate and the n-well implants are carried out. Then the mask is thinned, and a deep p implant is carried out with the thinned n-well mask in place. This prevents Vt shifts in FETs formed in the n-well adjacent the nwell-pwell interface. The thinned mask is then removed, a p-well mask is put in place, and the remainder of the p-well implants are carried out.
摘要翻译：形成逆行n井和p井的方法。在基板上形成第一掩模，并执行n阱注入。然后将掩模变薄，并用较薄的n面罩进行深度p植入。这防止了在n阱中形成的在n阱中形成的FET的Vt偏移。然后去除变薄的掩模，将p-阱掩模放置就位，并且执行其余的p阱注入。

84. 发明申请

US20130140513A1 THERMALLY CONFINED ELECTRODE FOR PROGRAMMABLE RESISTANCE MEMORY 有权
标题翻译：用于可编程电阻存储器的热电极
公开(公告)号：US20130140513A1
公开(公告)日：2013-06-06
申请号：US13310583
申请日：2011-12-02
申请人： Sheng-Chih Lai , Hsiang-Lan Lung , Matthew J. Breitwisch
发明人： Sheng-Chih Lai , Hsiang-Lan Lung , Matthew J. Breitwisch
IPC分类号： H01L47/00 , H01L21/02
CPC分类号： H01L45/06 , H01L27/2463 , H01L45/1233 , H01L45/126 , H01L45/16
摘要： A memory device includes a plurality of side-wall electrodes formed on a first side-wall of a trench within an insulating layer over a first plurality of contacts in an array of contacts in a substrate. The plurality of side-wall electrodes contact respective top surfaces of the first plurality of contacts. The side-wall electrodes respectively comprise a layer of tantalum nitride, having a composition TaxNy, where y is greater than x, and a layer of electrode material having a lower electrical resistivity and a lower thermal resistivity than the layer of tantalum nitride. Top surfaces of the plurality of side-wall electrodes contact memory material. A second plurality of side-wall electrodes may be formed on a second side-wall of the trench over a second plurality of contacts in the array of contacts.
摘要翻译：存储器件包括多个侧壁电极，形成在绝缘层中的沟槽的第一侧壁上，在衬底中的触点阵列中的第一多个触点上。多个侧壁电极接触第一多个触点的相应顶表面。侧壁电极分别包括氮化钽层，其具有组成为TaxNy，其中y大于x，并且电极材料层具有比氮化钽层更低的电阻率和更低的热阻率。多个侧壁电极的顶表面接触记忆材料。第二多个侧壁电极可以形成在沟槽阵列中的第二多个触点上的沟槽的第二侧壁上。

85. 发明授权

US08383501B2 Vertical field effect transistor arrays and methods for fabrication thereof 有权
标题翻译：垂直场效应晶体管阵列及其制造方法
公开(公告)号：US08383501B2
公开(公告)日：2013-02-26
申请号：US13185055
申请日：2011-07-18
申请人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L21/28
CPC分类号： H01L21/823487 , H01L27/088
摘要： Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.
摘要翻译：垂直场效应晶体管半导体结构和用于制造垂直场效应晶体管半导体结构的方法提供半导体柱阵列。半导体柱阵列中的每个半导体柱的每个垂直部分具有大于与相邻半导体柱的间隔距离的线宽。或者，阵列可以包括具有不同线宽的半导体柱，任选地在上述线宽和间隔距离限制的上下文中。用于制造半导体柱阵列的方法使用最小光刻尺寸的柱掩模层，其在被用作蚀刻掩模之前用至少一个间隔层环形增强。

86. 发明授权

US08378328B2 Phase change memory random access device using single-element phase change material 失效
标题翻译：相变存储器随机存取装置采用单元相变材料
公开(公告)号：US08378328B2
公开(公告)日：2013-02-19
申请号：US12036215
申请日：2008-02-22
申请人： Matthew J. Breitwisch , Chieh-Fang Chen , Yi-Chou Chen , Chung H. Lam , Simone Raoux
发明人： Matthew J. Breitwisch , Chieh-Fang Chen , Yi-Chou Chen , Chung H. Lam , Simone Raoux
IPC分类号： H01L29/02 , H01L47/00
CPC分类号： H01L45/06 , G11C13/0004 , H01L27/2436 , H01L45/1226 , H01L45/14
摘要： A phase change memory cell with a single element phase change thin film layer; and a first electrode and a second electrode coupled to the single element phase change thin film layer. A current flows from the first electrode to the single element phase change thin film layer, and through to the second electrode. The single element phase change thin film layer includes a single element phase change material. The single element phase change thin film layer can be less than 5 nanometers thick. The temperature of crystallization of the single element phase change material can be controlled by its thickness. In one embodiment, the single element phase change thin film layer is configured to be amorphous at room temperature (25 degrees Celsius). In one embodiment, the single element phase change thin film layer is comprised of Antimony (Sb).
摘要翻译：具有单个元件相变薄膜层的相变存储单元; 以及耦合到单个元件相变薄膜层的第一电极和第二电极。 A电流从第一电极流向单一元件相变薄膜层，并通过第二电极。单元相变薄膜层包括单一元素相变材料。单相相变薄膜层可以小于5纳米厚。单元相变材料的结晶温度可以通过其厚度来控制。在一个实施例中，单个元件相变薄膜层被配置为在室温（25摄氏度）下是无定形的。在一个实施例中，单元相变薄膜层由锑（Sb）组成。

87. 发明申请

US20130001500A1 PORE PHASE CHANGE MATERIAL CELL FABRICATED FROM RECESSED PILLAR 有权
公开(公告)号：US20130001500A1
公开(公告)日：2013-01-03
申请号：US13612552
申请日：2012-09-12
申请人： Alejandro G. Schrott , Chung H. Lam , Eric A. Joseph , Matthew J. Breitwisch , Roger W. Cheek
发明人： Alejandro G. Schrott , Chung H. Lam , Eric A. Joseph , Matthew J. Breitwisch , Roger W. Cheek
IPC分类号： H01L45/00
CPC分类号： H01L45/1625 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1616 , H01L45/165 , H01L45/1666
摘要： A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.

88. 发明申请

US20130001499A1 Compressive Structure for Enhancing Contact of Phase Change Material Memory Cells 审中-公开
标题翻译：用于增强相变材料记忆单元接触的压缩结构
公开(公告)号：US20130001499A1
公开(公告)日：2013-01-03
申请号：US13171210
申请日：2011-06-28
申请人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L45/00 , H01L21/06 , H01L21/62
CPC分类号： H01L45/06 , H01L45/144 , H01L45/1616 , H01L45/1683
摘要： A process for manufacturing a PCM device comprises forming a dielectric, producing a via in the dielectric starting at an area on the surface of the dielectric by forming a via opening in the area and extending the opening into the dielectric toward and then terminating at an electrode comprising a first electrode in the dielectric. We form a spacer layer contiguous with the side walls of the via and fill the via with a PCM. We then remove the surface of the dielectric to leave a PCM cusp at the opening of the via, cap the PCM cusp with a low density capping film; densify the PCM and capping film to obtain a high density capping film that exerts compressive pressure on the high density PCM in a direction toward the first electrode to enhance electrical contact between the PCM and the first electrode.
摘要翻译：一种用于制造PCM器件的方法包括形成电介质，通过在该区域中形成通孔开口，在电介质的表面上的区域开始在电介质中产生通孔，并将该开口延伸到电介质中然后终止于电极包括电介质中的第一电极。我们形成与通孔的侧壁相邻的间隔层，并用PCM填充通孔。然后我们将电介质的表面去除，以在通孔的开口处留下PCM尖点，用低密度封盖膜盖住PCM尖端; 密封PCM和封盖膜以获得高密度封盖膜，其在朝向第一电极的方向上对高密度PCM施加压缩压力，以增强PCM与第一电极之间的电接触。

89. 发明授权

US08283202B2 Single mask adder phase change memory element 有权
标题翻译：单掩模加法器相变存储元件
公开(公告)号：US08283202B2
公开(公告)日：2012-10-09
申请号：US12549997
申请日：2009-08-28
申请人： Matthew J. Breitwisch , Chandrasekharan Kothandaraman , Chung H. Lam
发明人： Matthew J. Breitwisch , Chandrasekharan Kothandaraman , Chung H. Lam
IPC分类号： H01L45/00
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/1683
摘要： A method of fabricating a phase change memory element within a semiconductor structure includes etching an opening to an upper surface of a bottom electrode, the opening being formed of a height equal to a height of a metal region at a same layer within the semiconductor structure, depositing phase change material within the opening, recessing the phase change material within the opening, and forming a top electrode on the recessed phase change material.
摘要翻译：在半导体结构内制造相变存储元件的方法包括蚀刻到底部电极的上表面的开口，该开口由等于半导体结构内同一层的金属区域的高度的高度形成，在开口内沉积相变材料，使开关内的相变材料凹陷，并在凹陷相变材料上形成顶部电极。

90. 发明授权

US08278197B2 Method to tailor location of peak electric field directly underneath an extension spacer for enhanced programmability of a prompt-shift device 有权
标题翻译：方法可以直接在扩展垫片下方定制峰值电场的位置，以提高快速移位装置的可编程性
公开(公告)号：US08278197B2
公开(公告)日：2012-10-02
申请号：US12130460
申请日：2008-05-30
申请人： Matthew J. Breitwisch , Roger W. Cheek , Jeffrey B. Johnson , Chung H. Lam , Beth A. Rainey , Michael J. Zierak
发明人： Matthew J. Breitwisch , Roger W. Cheek , Jeffrey B. Johnson , Chung H. Lam , Beth A. Rainey , Michael J. Zierak
IPC分类号： H01L21/265
CPC分类号： H01L29/66477 , H01L21/26513 , H01L21/26586 , H01L21/266 , H01L29/1083 , H01L29/6659 , H01L29/66833 , H01L29/7834 , H01L29/792
摘要： The invention provides a method to enhance the programmability of a prompt-shift device, which reduces the programming time to sub-millisecond times, by altering the extension and halo implants, instead of simply omitting the same from one side of the device as is the case in the prior art prompt-shift devices. The invention includes an embodiment in which no additional masks are employed, or one additional mask is employed. The altered extension implant is performed at a reduced ion dose as compared to a conventional extension implant process, while the altered halo implant is performed at a higher ion dose than a conventional halo implant. The altered halo/extension implant shifts the peak of the electrical field to under an extension dielectric spacer.
摘要翻译：本发明提供了一种通过改变扩展和光晕注入来提高快速移位设备的可编程性的方法，其将编程时间缩短到几毫秒，而不是从设备的一侧简单地省略它现有技术中的瞬时移位装置。本发明包括其中不使用附加掩模的实施例，或者采用一个附加掩模。与常规的延伸植入过程相比，改变的延伸植入物以降低的离子剂量进行，而改变的晕轮植入物以比常规的晕轮植入物更高的离子剂量进行。改变的光晕/延伸注入将电场的峰值移动到延伸电介质间隔物下方。

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