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81. 发明申请

US20100002499A1 PHASE CHANGE MEMORY PROGRAMMING METHOD WITHOUT RESET OVER-WRITE 有权
标题翻译：相位改变记忆编程方法，无复位写入
公开(公告)号：US20100002499A1
公开(公告)日：2010-01-07
申请号：US12166934
申请日：2008-07-02
申请人： Matthew J. Breitwisch , Chung H. Lam
发明人： Matthew J. Breitwisch , Chung H. Lam
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0064 , G11C2013/0076 , G11C2013/0078 , G11C2013/0092
摘要： A method for programming a phase change memory device that avoids RESET overwrite. The method partially comprised of applying a reset write current pulse through the phase change memory element such that the reset write current pulse produces a voltage drop across the phase change memory element less than a reset threshold voltage and greater than a set threshold voltage. The reset write current pulse writing a RESET state to the phase change memory cell. The method additionally comprised of applying a set write current pulse through the phase change memory element such that the set write current pulse produces a voltage drop across the phase change memory element that is equal to or greater than the reset threshold voltage. The set write current pulse writing a SET state to the phase change memory cell.
摘要翻译：一种编程避免RESET重写的相变存储器件的方法。所述方法部分地包括通过将所述复位写入电流脉冲施加到所述相变存储元件，使得所述复位写入电流脉冲在所述相变存储元件上产生小于复位阈值电压并大于设定阈值电压的电压降。复位写入电流脉冲将RESET状态写入相变存储单元。该方法还包括通过相变存储元件施加设置的写入电流脉冲，使得所设置的写入电流脉冲在相变存储器元件上产生等于或大于复位阈值电压的电压降。该设定的写入电流脉冲将SET状态写入相变存储单元。

82. 发明申请

US20090305492A1 VERTICAL FIELD EFFECT TRANSISTOR ARRAYS AND METHODS FOR FABRICATION THEREOF 有权
标题翻译：垂直场效应晶体管阵列及其制造方法
公开(公告)号：US20090305492A1
公开(公告)日：2009-12-10
申请号：US12541495
申请日：2009-08-14
申请人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L21/28
CPC分类号： H01L21/823487 , H01L27/088
摘要： Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.
摘要翻译：垂直场效应晶体管半导体结构和用于制造垂直场效应晶体管半导体结构的方法提供半导体柱阵列。半导体柱阵列中的每个半导体柱的每个垂直部分具有大于与相邻半导体柱的间隔距离的线宽。或者，阵列可以包括具有不同线宽的半导体柱，任选地在上述线宽和间隔距离限制的上下文中。用于制造半导体柱阵列的方法使用最小光刻尺寸的柱掩模层，其在被用作蚀刻掩模之前用至少一个间隔层环形增强。

83. 发明授权

US07602631B2 Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition 有权
标题翻译：利用测量时间延迟作为电平定义的特征参数的多电平存储单元
公开(公告)号：US07602631B2
公开(公告)日：2009-10-13
申请号：US11857356
申请日：2007-09-18
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C11/565 , G11C11/5628 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C16/32 , G11C2013/0054
摘要： A memory array and computer program product for operating a memory cell and memory array. An embodiment of the invention entails receiving a binary value to be stored by a memory cell. A determining operation determines a target discharge time corresponding to the binary value. The target discharge time being the time needed to discharge a pre-charged circuit through the said memory cell to a predetermined level. A storing operation stores a characteristic parameter in the memory cell such that an electron discharge time through an electronic circuit formed, at least partially, by the memory cell, is substantially equal to the target discharge time.
摘要翻译：用于操作存储器单元和存储器阵列的存储器阵列和计算机程序产品。本发明的实施例需要接收由存储器单元存储的二进制值。确定操作确定对应于二进制值的目标放电时间。目标放电时间是将预充电电路通过所述存储单元放电至预定水平所需的时间。存储操作将特征参数存储在存储单元中，使得通过至少部分地由存储单元形成的电子电路的电子放电时间基本上等于目标放电时间。

84. 发明申请

US20090212274A1 PHASE CHANGE MEMORY RANDOM ACCESS DEVICE USING SINGLE-ELEMENT PHASE CHANGE MATERIAL 失效
标题翻译：使用单元相变材料的相变存储随机存取设备
公开(公告)号：US20090212274A1
公开(公告)日：2009-08-27
申请号：US12036215
申请日：2008-02-22
申请人： Matthew J. Breitwisch , Chieh-Fang Chen , Yi-Chou Chen , Chung H. Lam , Simone Raoux
发明人： Matthew J. Breitwisch , Chieh-Fang Chen , Yi-Chou Chen , Chung H. Lam , Simone Raoux
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , G11C13/0004 , H01L27/2436 , H01L45/1226 , H01L45/14
摘要： A phase change memory cell with a single element phase change thin film layer; and a first electrode and a second electrode coupled to the single element phase change thin film layer. A current flows from the first electrode to the single element phase change thin film layer, and through to the second electrode. The single element phase change thin film layer includes a single element phase change material. The single element phase change thin film layer can be less than 5 nanometers thick. The temperature of crystallization of the single element phase change material can be controlled by its thickness. In one embodiment, the single element phase change thin film layer is configured to be amorphous at room temperature (25 degrees Celsius). In one embodiment, the single element phase change thin film layer is comprised of Antimony (Sb).
摘要翻译：具有单个元件相变薄膜层的相变存储单元; 以及耦合到单个元件相变薄膜层的第一电极和第二电极。 A电流从第一电极流向单一元件相变薄膜层，并通过第二电极。单元相变薄膜层包括单一元素相变材料。单相相变薄膜层可以小于5纳米厚。单元相变材料的结晶温度可以通过其厚度来控制。在一个实施例中，单个元件相变薄膜层被配置为在室温（25摄氏度）下是无定形的。在一个实施例中，单元相变薄膜层由锑（Sb）组成。

85. 发明申请

US20090212272A1 SELF-CONVERGING BOTTOM ELECTRODE RING 失效
标题翻译：自适应底部电极环
公开(公告)号：US20090212272A1
公开(公告)日：2009-08-27
申请号：US12036372
申请日：2008-02-25
申请人： Matthew J. Breitwisch , Chung H. Lam , Hsiang-Lan Lung
发明人： Matthew J. Breitwisch , Chung H. Lam , Hsiang-Lan Lung
IPC分类号： H01L21/06 , H01L47/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675 , H01L45/1683 , Y10S438/90
摘要： A method and memory cell including self-converged bottom electrode ring. The method includes forming a step spacer, a top insulating layer, an intermediate insulating layer, and a bottom insulating layer above a substrate. The method includes forming a step spacer within the top insulating layer and the intermediate insulating layer. The step spacer size is easily controlled. The method also includes forming a passage in the bottom insulating layer with the step spacer as a mask. The method includes forming bottom electrode ring within the passage comprising a cup-shaped outer conductive layer within the passage and forming an inner insulating layer within the cup-shaped outer conductive layer. The method including forming a phase change layer above the bottom electrode ring and a top electrode above the bottom electrode ring.
摘要翻译：一种包括自会聚底电极环的方法和存储单元。该方法包括在衬底上形成台阶间隔物，顶部绝缘层，中间绝缘层和底部绝缘层。该方法包括在顶部绝缘层和中间绝缘层内形成台阶间隔物。台阶垫片尺寸易于控制。该方法还包括在步骤间隔物作为掩模的底部绝缘层中形成通道。所述方法包括在所述通道内形成底部电极环，所述通道包括所述通道内的杯形外部导电层，并且在所述杯形外部导电层内形成内部绝缘层。该方法包括在底部电极环上方形成相变层和在底部电极环上方形成顶部电极。

86. 发明申请

US20090189731A1 CROSS POINT SWITCH USING PHASE CHANGE MATERIAL 有权
标题翻译：使用相变材料的交点切换
公开(公告)号：US20090189731A1
公开(公告)日：2009-07-30
申请号：US12106539
申请日：2008-04-21
申请人： Matthew J. Breitwisch , Chung H. Lam , Prabhakar Kudva
发明人： Matthew J. Breitwisch , Chung H. Lam , Prabhakar Kudva
IPC分类号： H01H37/12 , H01H37/32
CPC分类号： H03K19/173
摘要： A cross-point switch and cross-point switch fabric utilizing phase change material, and method of operating the same. The cross-point switch includes a phase change cross-point circuit containing a plurality of terminal nodes connected to a central node. The connections between the terminal nodes and the central nodes are regulated by phase change switches comprised of a phase change material. The phase change switches being controlled by heating elements capable of melting or crystallizing the phase change material in the phase change switch. The heating elements are operated by a separate heating circuit. Each individual heating element is regulated by an individual transistor.
摘要翻译：使用相变材料的交叉点开关和交叉点开关织物及其操作方法。交叉点开关包括包含连接到中央节点的多个终端节点的相变交叉点电路。终端节点和中心节点之间的连接由相变材料组成的相变开关来调节。相变开关由能够在相变开关中熔化或结晶相变材料的加热元件控制。加热元件由单独的加热回路操作。每个单独的加热元件由单个晶体管调节。

87. 发明授权

US07560721B1 Phase change material with filament electrode 有权
标题翻译：相变材料与灯丝电极
公开(公告)号：US07560721B1
公开(公告)日：2009-07-14
申请号：US12035237
申请日：2008-02-21
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott , Gerhard Ingmar Meijer
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott , Gerhard Ingmar Meijer
IPC分类号： H01L47/00
CPC分类号： H01L45/141 , G11C13/0004 , G11C13/0007 , G11C2213/52 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/1246 , H01L45/145
摘要： The present invention, in one embodiment, provides a memory device that includes a phase change memory cell; a first electrode; and a layer of filamentary resistor material positioned between the phase change memory cell and the first electrode, wherein at least one bistable conductive filamentary pathway is present in at least a portion of the layer of filamentary resistor material that provides electrical communication between the phase change memory cell and the first electrode.
摘要翻译：本发明在一个实施例中提供了一种包括相变存储单元的存储器件; 第一电极; 以及位于所述相变存储器单元和所述第一电极之间的丝状电阻材料层，其中在所述丝状电阻器材料层的至少一部分中存在至少一个双稳态导电丝状通道，其提供所述相变存储器电池和第一电极。

88. 发明申请

US20090111228A1 SELF ALIGNED RING ELECTRODES 有权
标题翻译：自对准环电极
公开(公告)号：US20090111228A1
公开(公告)日：2009-04-30
申请号：US11924073
申请日：2007-10-25
申请人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott , Brandon Yee
发明人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott , Brandon Yee
IPC分类号： H01L21/33
CPC分类号： H01L21/76843 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/148 , H01L45/16 , H01L45/1675 , H01L45/1683
摘要： The present invention in one embodiment provides a method of manufacturing an electrode that includes providing at least one metal stud positioned in a via extending into a first dielectric layer, wherein an electrically conductive liner is positioned between at least a sidewall of the via and the at least one metal stud; recessing an upper surface of the at least one metal stud below an upper surface of the first dielectric layer to provide at least one recessed metal stud; and forming a second dielectric atop the at least one recessed metal stud, wherein an upper surface of the electrically conductive liner is exposed.
摘要翻译：本发明在一个实施例中提供了一种制造电极的方法，其包括提供定位在延伸到第一介电层中的通孔中的至少一个金属柱，其中导电衬垫定位在通孔的至少侧壁和在最少一个金属螺柱; 将所述至少一个金属螺柱的上表面凹陷在所述第一介电层的上表面下方，以提供至少一个凹入的金属柱; 以及在所述至少一个凹入的金属螺柱的顶部上形成第二电介质，其中所述导电衬垫的上表面被暴露。

89. 发明申请

US20090073790A1 MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION 有权
标题翻译：多级存储单元利用测量时间延迟作为等级定义的特征参数
公开(公告)号：US20090073790A1
公开(公告)日：2009-03-19
申请号：US11857332
申请日：2007-09-18
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
IPC分类号： G11C7/00
CPC分类号： G11C11/565 , G11C11/5628 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C2013/0054
摘要： A method for operating a memory cell and memory array. The method of memory cell operation entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage. A word-line in the electronic circuit is then activated. A discharging operation discharges the bit-line capacitor through the said memory cell in the electronic circuit to the word-line. Additionally, an electron discharge time measurement is started when the word-line is activated. The electron discharge time measurement is stopped when the voltage level in the bit-line falls below a pre-defined reference voltage. A determining operation determines the binary value from the measured electron discharge time.
摘要翻译：一种用于操作存储单元和存储器阵列的方法。存储单元操作的方法需要接收读取存储在存储单元中的二进制值的请求。预充电操作将由存储器单元形成的电子电路中的位线电容器预先充电到预充电电压。然后激活电子电路中的字线。放电操作通过电子电路中的所述存储单元将位线电容器放电到字线。此外，当字线被激活时，电子放电时间测量开始。当位线中的电压电平低于预定义的参考电压时，停止电子放电时间测量。确定操作根据测量的电子放电时间确定二进制值。

90. 发明授权

US07485487B1 Phase change memory cell with electrode 有权
标题翻译：带电极的相变存储单元
公开(公告)号：US07485487B1
公开(公告)日：2009-02-03
申请号：US11970207
申请日：2008-01-07
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683 , H01L45/1691
摘要： The present invention in one embodiment provides a method of forming a memory device including providing a first dielectric layer including at least one via containing a metal stud; providing a second dielectric layer atop the first dielectric layer; recessing the metal stud to expose a sidewall of the via; etching the sidewall of the via in the first dielectric layer with a isotropic etch step to produce an undercut region extending beneath a portion of the second dielectric layer; forming a conformal insulating layer on at least the portion of the second dielectric layer overlying the undercut region to provide a keyhole; etching the conformal insulating layer with an anisotropic etch to provide a collar that exposes the metal stud; forming a barrier metal within the collar in contact with the metal stud; and forming a phase change material in contact with the barrier metal.
摘要翻译：本发明在一个实施例中提供了一种形成存储器件的方法，该存储器件包括：提供包括至少一个通孔的第一介电层，所述通孔包含金属螺柱; 在所述第一电介质层的顶部提供第二电介质层; 使金属螺柱凹陷以暴露通孔的侧壁; 用各向同性蚀刻步骤蚀刻第一介电层中的通孔的侧壁，以产生在第二介电层的一部分下方延伸的底切区域; 在覆盖所述底切区域的所述第二介电层的至少一部分上形成保形绝缘层以提供锁眼; 用各向异性蚀刻蚀刻保形绝缘层以提供露出金属螺柱的套环; 在所述套环内形成与所述金属螺栓接触的阻挡金属; 并形成与阻挡金属接触的相变材料。

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