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81. 发明申请

US20060102290A1 Wafer support plate, holding method of thin wafer, and manufacturing method of semiconductor device 审中-公开
标题翻译：晶片支撑板，薄晶片保持方法及半导体器件的制造方法
公开(公告)号：US20060102290A1
公开(公告)日：2006-05-18
申请号：US11221763
申请日：2005-09-09
申请人： Susumu Harada , Chiaki Takubo , Kenji Takahashi , Hideo Aoki , Hideo Numata , Hisashi Kaneko , Hirokazu Ezawa , Mie Matsuo , Hiroshi Ikenoue , Ichiro Omura
发明人： Susumu Harada , Chiaki Takubo , Kenji Takahashi , Hideo Aoki , Hideo Numata , Hisashi Kaneko , Hirokazu Ezawa , Mie Matsuo , Hiroshi Ikenoue , Ichiro Omura
IPC分类号： B32B37/00
CPC分类号： H01L21/6835 , H01L21/76898
摘要： A wafer supporting plate is formed of a glass or a resin which can permeate ultraviolet rays and has a nearly disk shape. An outer diameter of the wafer supporting plate is larger than that of the semiconductor wafer which is supported. In the wafer supporting plate, a plurality of openings are formed to correspond to plural through holes of the semiconductor wafer. The opening has an open area larger than an open area of the through hole, that is, has a larger diameter.
摘要翻译：晶片支撑板由可以渗透紫外线并具有近似圆盘形状的玻璃或树脂形成。晶片支撑板的外径大于被支撑的半导体晶片的外径。在晶片支撑板中，形成多个开口以对应于半导体晶片的多个通孔。开口具有比通孔的开口面积大的开口面积，即具有较大的直径。

82. 发明申请

US20060071267A1 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US20060071267A1
公开(公告)日：2006-04-06
申请号：US11265294
申请日：2005-11-03
申请人： Wataru Saito , Ichiro Omura , Tsuneo Ogura
发明人： Wataru Saito , Ichiro Omura , Tsuneo Ogura
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0653 , H01L29/66712 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a power semiconductor device, including a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type which are alternately and laterally arranged on the first semiconductor layer and, a fourth semiconductor layer of the second conductivity type selectively formed in the surface regions of the second and third semiconductor layers, a fifth semiconductor layer of the first conductivity type selectively formed in the surface region of the fourth semiconductor layer, and a control electrode formed on the surfaces of the second, fourth and fifth semiconductor layers, in which a layer thickness ratio A is given by the expression: 0
摘要翻译：公开了一种功率半导体器件，包括第一导电类型的第一半导体层，第一导电类型的第二半导体层和第二导电类型的第三半导体层，其交替地和横向地布置在第一半导体层上，选择性地形成在第二和第三半导体层的表面区域中的第二导电类型的第四半导体层，选择性地形成在第四半导体层的表面区域中的第一导电类型的第五半导体层和形成在第二半导体层上的控制电极第二半导体层，第四半导体层和第五半导体层的表面，其中层厚度比A由以下表达式给出：<？in-line-formula description =“In-line Formulas”end =“lead”？> 0 其中t是第一半导体层的厚度，d是这个半导体层。

83. 发明申请

US20060034114A1 Gate driving circuit and gate driving method of power MOSFET 失效
标题翻译：功率MOSFET的栅极驱动电路和栅极驱动方法
公开(公告)号：US20060034114A1
公开(公告)日：2006-02-16
申请号：US11189704
申请日：2005-07-27
申请人： Ichiro Omura
发明人： Ichiro Omura
IPC分类号： G11C11/24
CPC分类号： H03K17/04123 , H03K17/6877
摘要： A gate driving circuit and method which increases the switching frequency by use of a switching control circuit which controls operations of a first, second, third, and fourth switches. The switching control circuit performs switching control of a power MOSFET when the MOSFET is to be turned on, so that a period exists when the first and fourth switches are simultaneously ON. The switching circuit also performs switching control when a MOSFET is to be turned off, so that a period exists when the second and third switches are simultaneously ON.
摘要翻译：一种通过使用控制第一，第二，第三和第四开关的操作的开关控制电路来提高开关频率的栅极驱动电路和方法。当MOSFET接通时，开关控制电路执行功率MOSFET的开关控制，从而当第一和第四开关同时导通时，存在周期。当MOSFET关闭时，开关电路还执行开关控制，从而当第二和第三开关同时接通时，存在周期。

84. 发明授权

US06995426B2 Semiconductor device having vertical metal insulator semiconductor transistors having plural spatially overlapping regions of different conductivity type 有权
标题翻译：具有垂直金属绝缘体半导体晶体管的半导体器件具有不同导电类型的多个空间重叠区域
公开(公告)号：US06995426B2
公开(公告)日：2006-02-07
申请号：US10327937
申请日：2002-12-26
申请人： Hideki Okumura , Hitoshi Kobayashi , Masanobu Tsuchitani , Akihiko Osawa , Wataru Saito , Masakazu Yamaguchi , Ichiro Omura
发明人： Hideki Okumura , Hitoshi Kobayashi , Masanobu Tsuchitani , Akihiko Osawa , Wataru Saito , Masakazu Yamaguchi , Ichiro Omura
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/7802
摘要： A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.
摘要翻译：半导体器件包括形成在第一导电类型的半导体层中的扩散区域。扩散区域分别包括第一和第二导电类型的第一和第二杂质扩散区域。扩散区域具有由第一和第二杂质扩散区域的杂质浓度限定的第一和第二区域。第一和第二区域之间的结点形成在第一和第二杂质扩散区域彼此重叠的部分中。在第一或第二区域的半导体层的平面方向上的杂质浓度的周期小于半导体层的平面方向上的构成第一或第二区域的第一和第二杂质扩散区域的最大宽度第二区。

85. 发明申请

US20050224945A1 Power semiconductor device package 失效
标题翻译：功率半导体器件封装
公开(公告)号：US20050224945A1
公开(公告)日：2005-10-13
申请号：US10867758
申请日：2004-06-16
申请人： Wataru Saito , Ichiro Omura
发明人： Wataru Saito , Ichiro Omura
IPC分类号： H01L25/07 , H01L23/02 , H01L23/495 , H01L25/18
CPC分类号： H01L24/41 , H01L23/49575 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L25/074 , H01L2224/32245 , H01L2224/37124 , H01L2224/37147 , H01L2224/40245 , H01L2224/40247 , H01L2224/45014 , H01L2224/45124 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73221 , H01L2224/73253 , H01L2224/73257 , H01L2224/83801 , H01L2224/84801 , H01L2225/06562 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2224/45147 , H01L2924/00012
摘要： A power semiconductor device package according to one aspect of the present invention comprises: a plurality of power semiconductor chips which are arranged in a laminated structure so that the plurality of power semiconductor chips are opposing to each other at the surfaces with the same electrical structures, and which are connected in parallel to one another, and are sealed in a sealing resin as one body.
摘要翻译：根据本发明的一个方面的功率半导体器件封装包括：多个功率半导体芯片，它们以层叠结构布置，使得多个功率半导体芯片在具有相同电结构的表面处彼此相对，并且彼此并联连接，并且作为一体被密封在密封树脂中。

86. 发明授权

US06933544B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US06933544B2
公开(公告)日：2005-08-23
申请号：US10967166
申请日：2004-10-19
申请人： Wataru Saito , Ichiro Omura , Hiromichi Ohashi
发明人： Wataru Saito , Ichiro Omura , Hiromichi Ohashi
IPC分类号： H01L29/20 , H01L29/40 , H01L29/417 , H01L29/739 , H01L29/80 , H01L29/861 , H01L31/0336
CPC分类号： H01L29/802 , H01L29/2003 , H01L29/402 , H01L29/417 , H01L29/4175 , H01L29/861
摘要： A power semiconductor device including a non-doped GaN channel layer, an n-type Al0.2Ga0.8N barrier layer formed on the channel layer, a p-type Al0.1Ga0.9N semiconductor layer selectively formed on the barrier layer, a drain electrode positioned at one of both sides of the semiconductor layer and formed on the barrier layer, an insulating film formed on the barrier layer adjacent to the semiconductor layer between at least semiconductor layer and drain electrode, and a field plate electrode formed on the insulating film.
摘要翻译：包括形成在沟道层上的非掺杂GaN沟道层，n型Al 0.2 Ga 0.8 N阻挡层的功率半导体器件，p型Al < 选择性地形成在阻挡层上的半导体层，位于半导体层的两侧之一并形成在阻挡层上的漏电极，形成绝缘膜在至少半导体层和漏电极之间的与半导体层相邻的阻挡层上，以及形成在绝缘膜上的场极板电极。

87. 发明授权

US06930352B2 Insulated gate semiconductor device 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US06930352B2
公开(公告)日：2005-08-16
申请号：US10463613
申请日：2003-06-18
申请人： Wataru Saito , Ichiro Omura , Satoshi Aida
发明人： Wataru Saito , Ichiro Omura , Satoshi Aida
IPC分类号： H01L29/06 , H01L29/08 , H01L29/10 , H01L29/739 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/7397 , H01L29/7813
摘要： An insulated gate semiconductor device includes a control electrode having a trench type structure formed on the surface of a first semiconductor layer of a first conductivity type via a gate insulation film and disposed in a lattice shape, the control electrode having a plurality of first control electrode sections and a plurality of second control electrode sections which intersect with the plurality of first control electrode sections, respectively, and a plurality of fifth semiconductor layers of a second conductivity type which are provided on an interface of the first semiconductor layer in contact with the plurality of second control electrode sections, and connected to at least one of a plurality of second semiconductor layers of the second conductivity type, the fifth semiconductor layers having impurity concentration lower than that of the plurality of second semiconductor layers.
摘要翻译：一种绝缘栅半导体器件，包括：控制电极，具有通过栅极绝缘膜形成在第一导电类型的第一半导体层的表面上并且格栅形状的沟槽型结构，所述控制电极具有多个第一控制电极分别与多个第一控制电极部分相交的多个第二控制电极部分和多个第二导电类型的第五半导体层，其设置在第一半导体层的与多个第一控制电极部分接触的界面上的第二控制电极部分，并且连接到第二导电类型的多个第二半导体层中的至少一个，所述第五半导体层的杂质浓度低于多个第二半导体层的杂质浓度。

88. 发明授权

US06919610B2 Power semiconductor device having RESURF layer 失效
标题翻译：具有RESURF层的功率半导体器件
公开(公告)号：US06919610B2
公开(公告)日：2005-07-19
申请号：US10714916
申请日：2003-11-18
申请人： Wataru Saitoh , Ichiro Omura
发明人： Wataru Saitoh , Ichiro Omura
IPC分类号： H01L21/265 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/78 , H01L23/58
CPC分类号： H01L29/7811 , H01L21/26586 , H01L21/3247 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/66712 , H01L29/7802 , H01L29/7816 , H01L29/7824 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including a drain layer having a first conductivity type, a drift layer having the first conductivity type, which is formed on the drain layer and has an impurity concentration lower than that in the drain layer, and a RESURF layer having a second conductivity type and formed to extend from a surface of the drift layer into the drain layer, the RESURF layer forming a superjunction structure together with the drift layer and forming a depletion layer in the drift layer.
摘要翻译：一种半导体器件，包括具有第一导电类型的漏极层，具有第一导电类型的漂移层，其形成在漏极层上并且具有低于漏极层中的杂质浓度，以及具有第二导电性的RESURF层形成为从漂移层的表面延伸到漏极层，RESURF层与漂移层一起形成超结构结构，并在漂移层中形成耗尽层。

89. 发明申请

US20050098826A1 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050098826A1
公开(公告)日：2005-05-12
申请号：US11002638
申请日：2004-12-03
申请人： Masakazu Yamaguchi , Wataru Saito , Ichiro Omura , Masaru Izumisawa
发明人： Masakazu Yamaguchi , Wataru Saito , Ichiro Omura , Masaru Izumisawa
IPC分类号： H01L21/336 , H01L29/06 , H01L29/40 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/402 , H01L29/41741 , H01L29/66712 , H01L29/7802
摘要： A method of manufacturing a semiconductor device in which a trench groove is formed in a first conductivity type semiconductor layer, and a second conductivity type semiconductor layer is epitaxially grown so as to bury the trench groove. The second conductivity type semiconductor layer is then removed until a surface of the first conductivity type semiconductor layer is exposed. The first conductivity type semiconductor layer is epitaxially grown on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer such that the thickness of the first conductivity type semiconductor layer increases by a length which is substantially the same as a depth of the trench groove. The first conductivity type semiconductor layer is selectively removed such that the second conductivity type semiconductor layer is exposed, and the epitaxially growing of the second conductivity type semiconductor layer is repeated through selectively removing the first conductivity type semiconductor layer.
摘要翻译：一种制造半导体器件的方法，其中在第一导电类型半导体层中形成沟槽槽，并且外延生长第二导电类型半导体层以便埋入沟槽。然后去除第二导电类型半导体层直到露出第一导电类型半导体层的表面。在第一导电类型半导体层和第二导电类型半导体层上外延生长第一导电类型半导体层，使得第一导电类型半导体层的厚度增加与沟槽的深度基本相同的长度。选择性地去除第一导电型半导体层，使得露出第二导电类型半导体层，并且通过选择性地去除第一导电类型半导体层来重复第二导电类型半导体层的外延生长。

90. 发明授权

US06849880B1 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US06849880B1
公开(公告)日：2005-02-01
申请号：US10795325
申请日：2004-03-09
申请人： Wataru Saito , Ichiro Omura , Satoshi Aida
发明人： Wataru Saito , Ichiro Omura , Satoshi Aida
IPC分类号： H01L29/78 , H01L21/336 , H01L21/76 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/402 , H01L29/41775 , H01L29/42372 , H01L29/7813
摘要： A power semiconductor device includes second layers of a second conductivity type disposed in a first layer of a first conductivity type. The second layers extend in a depth direction and are arrayed at intervals. Third layers of the second conductivity type are disposed respectively in contact with the second layers. Fourth layers of the first conductivity type are respectively formed in surfaces of the third layers. A gate electrode faces, through a first insulating film, a channel region, which is each of portions of the third layers interposed between the fourth layers and the first layer. An additional electrode is disposed on each of the second layers through a second insulating film, and faces, through each of the second layers, the first main electrode. The additional electrode is electrically connected to the gate electrode.
摘要翻译：功率半导体器件包括设置在第一导电类型的第一层中的第二导电类型的第二层。第二层在深度方向上延伸并且以间隔排列。第二导电类型的第三层分别设置为与第二层接触。第一导电类型的第四层分别形成在第三层的表面中。栅电极通过第一绝缘膜面向通道区域，沟道区域是介于第四层和第一层之间的第三层的每个部分。附加电极通过第二绝缘膜设置在每个第二层上，并且通过每个第二层面向第一主电极。附加电极电连接到栅电极。

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