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81. 发明授权

US07763946B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07763946B2
公开(公告)日：2010-07-27
申请号：US11871570
申请日：2007-10-12
申请人： Yoshinori Tsuchiya , Masato Koyama
发明人： Yoshinori Tsuchiya , Masato Koyama
IPC分类号： H01L27/092
CPC分类号： H01L21/823835 , H01L21/28097 , H01L29/4975 , H01L29/517 , H01L29/665 , H01L29/7845
摘要： A semiconductor device includes: a substrate and a p-channel MIS transistor. The p-channel MIS transistor includes: an n-type semiconductor region formed in the substrate; p-type first source and drain regions formed at a distance from each other in the n-type semiconductor region; a first gate insulating film formed on the n-type semiconductor region between the first source region and the first drain region; and a first gate electrode formed on the first gate insulating film. The first gate electrode includes a first nickel silicide layer having a Ni/Si composition ratio of 1 or greater, and a silicide layer formed on the first nickel silicide layer. The silicide layer contains a metal having a larger absolute value of oxide formation energy than that of Si, and a composition ratio of the metal to Si is smaller than the Ni/Si composition ratio.
摘要翻译：半导体器件包括：衬底和p沟道MIS晶体管。 p沟道MIS晶体管包括：形成在衬底中的n型半导体区域; 在n型半导体区域中形成为彼此间隔一定距离的p型第一源极和漏极区域; 形成在所述第一源极区域和所述第一漏极区域之间的所述n型半导体区域上的第一栅极绝缘膜; 以及形成在第一栅极绝缘膜上的第一栅电极。第一栅电极包括Ni / Si组成比为1或更大的第一硅化镍层和形成在第一硅化镍层上的硅化物层。硅化物层含有氧化物形成能量绝对值高于Si的金属，金属与Si的组成比小于Ni / Si组成比。

82. 发明授权

US07667273B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07667273B2
公开(公告)日：2010-02-23
申请号：US11679417
申请日：2007-02-27
申请人： Masato Koyama , Yoshinori Tsuchiya
发明人： Masato Koyama , Yoshinori Tsuchiya
IPC分类号： H01L23/62
CPC分类号： H01L21/28273 , H01L21/26513 , H01L21/823842 , H01L21/823857 , H01L27/092 , H01L27/115 , H01L27/11521 , H01L29/66825 , H01L29/785 , H01L29/7881
摘要： A semiconductor device includes a p-channel MIS transistor. A p-channel MIS transistor includes; an n-type semiconductor layer formed on the substrate; first source/drain regions being formed in the n-type semiconductor layer and being separated from each other; a first gate insulating film being formed on the n-type semiconductor layer between the first source/drain regions, and containing silicon, oxygen, and nitrogen, or containing silicon and nitrogen; a first gate electrode formed above the first gate insulating film; and a first interfacial layer being formed at an interface between the first gate insulating film and the first gate electrode, and containing a 13-group element. The total number of metallic bonds in the 13-group element in the interfacial layer being larger than the total number of each of oxidized, nitrided, or oxynitrided bonds in the 13-group element in the interfacial layer.
摘要翻译：半导体器件包括p沟道MIS晶体管。 P沟道MIS晶体管包括：在该基板上形成的n型半导体层; 第一源极/漏极区域形成在n型半导体层中并彼此分离; 第一栅极绝缘膜，形成在第一源极/漏极区域之间的n型半导体层上，并且包含硅，氧和氮，或含有硅和氮; 形成在所述第一栅极绝缘膜上方的第一栅电极; 以及在所述第一栅极绝缘膜和所述第一栅电极之间的界面处形成并且包含13族元素的第一界面层。界面层中13组元素中的金属键总数大于界面层中13族元素中氧化，氮化或氧氮键的总数。

83. 发明申请

US20090032884A1 Semiconductor device, and method for manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090032884A1
公开(公告)日：2009-02-05
申请号：US12219571
申请日：2008-07-24
申请人： Yoshinori Tsuchiya , Masato Koyama , Masahiko Yoshiki
发明人： Yoshinori Tsuchiya , Masato Koyama , Masahiko Yoshiki
IPC分类号： H01L27/092 , H01L29/78
CPC分类号： H01L21/823835 , H01L27/1203 , H01L29/785
摘要： According to an aspect of the invention, a semiconductor device comprises: a N-channel MIS transistor comprising; a p-type semiconductor layer; a first gate insulation layer formed on the p-type semiconductor layer; a first gate electrode formed on the first gate insulation layer; and a first source-drain region formed in the p-type semiconductor layer where the first gate electrode is sandwiched along a direction of gate length. The first gate electrode comprises a crystal phase including a cubic crystal of NiSi2 which has a lattice constant of 5.39 angstroms to 5.40 angstroms.
摘要翻译：根据本发明的一个方面，半导体器件包括：N沟道MIS晶体管，包括： p型半导体层; 形成在p型半导体层上的第一栅绝缘层; 形成在所述第一栅极绝缘层上的第一栅电极; 以及形成在p型半导体层中的第一源极 - 漏极区，其中第一栅极沿着栅极长度的方向被夹持。第一栅电极包括晶体相，其包括具有5.39埃至5.40埃的晶格常数的NiSi 2的立方晶体。

84. 发明申请

US20080280405A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20080280405A1
公开(公告)日：2008-11-13
申请号：US12219096
申请日：2008-07-16
申请人： Yoshinori Tsuchiya , Masato Koyama
发明人： Yoshinori Tsuchiya , Masato Koyama
IPC分类号： H01L21/8234 , H01L21/8238
CPC分类号： H01L29/4958 , H01L21/2807 , H01L21/28079 , H01L21/28088 , H01L21/76802 , H01L21/76877 , H01L21/823807 , H01L21/823828 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L29/4966 , H01L29/4975 , H01L29/665
摘要： A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.
摘要翻译：半导体器件包括具有半导体层，栅电极，源极区，漏极区，元件隔离绝缘膜层和布线的半导体衬底。栅极包括在半导体层上形成有栅极绝缘膜的层压结构，形成在栅极绝缘膜上的金属或金属化合物以及形成在金属或金属化合物上的多晶硅层。源极区域和漏极区域形成在半导体衬底的表面部分上，并将栅电极夹在其间。元件分离绝缘膜层围绕半导体层。布线与栅电极的金属或金属化合物接触。

85. 发明申请

US20080185656A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080185656A1
公开(公告)日：2008-08-07
申请号：US11907353
申请日：2007-10-11
申请人： Masato Koyama , Yoshinori Tsuchiya , Seiji Inumiya
发明人： Masato Koyama , Yoshinori Tsuchiya , Seiji Inumiya
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28097 , H01L21/823835 , H01L21/823857 , H01L29/4975 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate; forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively; forming a first nickel silicide having a composition of Ni/Si
摘要翻译：可以提供一种半导体器件的制造方法，该半导体器件包括具有低阈值电压Vth和Ni-FUSI / SiON或高k栅极绝缘膜结构的CMIS。该方法包括：在衬底中形成彼此绝缘的p型半导体区域和n型半导体区域; 在p型和n型半导体区分别形成第一和第二栅极绝缘膜; 在所述第二栅极绝缘膜上形成具有Ni / Si <31/12以上的第一栅极绝缘膜的第一镍硅化物和具有Ni / Si> 31/12的组成的第二硅化镍; 以及通过使铝通过第一硅化镍扩散，在第一硅化镍和第一栅极绝缘膜之间的界面处分离铝。

86. 发明申请

US20060027879A1 Semiconductor device and method of manufacturing the same 失效
公开(公告)号：US20060027879A1
公开(公告)日：2006-02-09
申请号：US11244295
申请日：2005-10-06
申请人： Masato Koyama , Akira Nishiyama , Masamichi Suzuki , Yuuichi Kamimuta , Tsunehiro Ino
发明人： Masato Koyama , Akira Nishiyama , Masamichi Suzuki , Yuuichi Kamimuta , Tsunehiro Ino
IPC分类号： H01L29/76
CPC分类号： H01L21/823814 , H01L21/28097 , H01L21/823835 , H01L29/4975 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device can be manufactured which has a low resistance, and device characteristics of which do not vary. The semiconductor device includes a silicon layer, a gate dielectric film formed on the silicon layer, a gate electrode formed on the gate dielectric film and including a nitrided metal silicide layer which is partially crystallized, and source and drain regions formed in a surface region of the silicon layer at both sides of the gate electrode.

87. 发明授权

US06982467B2 Semiconductor device and method of manufacturing the same 失效
公开(公告)号：US06982467B2
公开(公告)日：2006-01-03
申请号：US10863204
申请日：2004-06-09
申请人： Masato Koyama , Akira Nishiyama , Masamichi Suzuki , Yuuichi Kamimuta , Tsunehiro Ino
发明人： Masato Koyama , Akira Nishiyama , Masamichi Suzuki , Yuuichi Kamimuta , Tsunehiro Ino
IPC分类号： H01L29/76
CPC分类号： H01L21/823814 , H01L21/28097 , H01L21/823835 , H01L29/4975 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device can be manufactured which has a low resistance, and device characteristics of which do not vary. The semiconductor device includes a silicon layer, a gate dielectric film formed on the silicon layer, a gate electrode formed on the gate dielectric film and including a nitrided metal silicide layer which is partially crystallized, and source and drain regions formed in a surface region of the silicon layer at both sides of the gate electrode.

88. 发明申请

US20050017305A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050017305A1
公开(公告)日：2005-01-27
申请号：US10863204
申请日：2004-06-09
申请人： Masato Koyama , Akira Nishiyama , Masamichi Suzuki , Yuuichi Kamimuta , Tsunehiro Ino
发明人： Masato Koyama , Akira Nishiyama , Masamichi Suzuki , Yuuichi Kamimuta , Tsunehiro Ino
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78 , H01L21/84 , H01L29/94
CPC分类号： H01L21/823814 , H01L21/28097 , H01L21/823835 , H01L29/4975 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device can be manufactured which has a low resistance, and device characteristics of which do not vary. The semiconductor device includes a silicon layer, a gate dielectric film formed on the silicon layer, a gate electrode formed on the gate dielectric film and including a nitrided metal silicide layer which is partially crystallized, and source and drain regions formed in a surface region of the silicon layer at both sides of the gate electrode.
摘要翻译：可以制造具有低电阻的半导体器件，其器件特性不变化。半导体器件包括硅层，形成在硅层上的栅极电介质膜，形成在栅极电介质膜上的栅电极，并且包括被部分结晶的氮化金属硅化物层，以及形成在栅电极两侧的硅层。

89. 发明申请

US20080224226A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20080224226A1
公开(公告)日：2008-09-18
申请号：US11858408
申请日：2007-09-20
申请人： Masamichi Suzuki , Masato Koyama
发明人： Masamichi Suzuki , Masato Koyama
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/28079 , H01L21/28097 , H01L21/28194 , H01L21/823842 , H01L29/165 , H01L29/47 , H01L29/4958 , H01L29/4975 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66636 , H01L29/7843 , H01L29/7845
摘要： A semiconductor device includes a semiconductor substrate, p-type first and n-type second semiconductor regions formed on the substrate so as to be insulated with each other, n-channel and p-channel MOS transistors formed on the first and second semiconductor regions, the n-channel transistor including a first pair of source/drain regions formed on the first semiconductor region, a first gate insulator formed in direct contact with the first semiconductor region and formed as an amorphous insulator containing at least La, and a first gate electrode formed on the first gate insulator, the p-channel MOS transistor including a second pair of source/drain regions formed opposite to each other on the second semiconductor region, a second gate insulator including a silicon oxide film and the amorphous insulating film formed thereon on the second semiconductor region, and a second gate electrode formed on the second gate insulator.
摘要翻译：半导体器件包括半导体衬底，形成在衬底上以彼此绝缘的p型第一和n型第二半导体区，形成在第一和第二半导体区上的n沟道和p沟道MOS晶体管，所述n沟道晶体管包括形成在所述第一半导体区域上的第一对源极/漏极区域，与所述第一半导体区域直接接触形成并形成为至少包含La的非晶绝缘体的第一栅极绝缘体和第一栅极电极形成在所述第一栅极绝缘体上的所述p沟道MOS晶体管，包括在所述第二半导体区域上彼此相对形成的第二对源极/漏极区域，包括氧化硅膜的第二栅极绝缘体和在其上形成的非晶绝缘膜第二半导体区域和形成在第二栅极绝缘体上的第二栅电极。

90. 发明授权

US07075158B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07075158B2
公开(公告)日：2006-07-11
申请号：US11244295
申请日：2005-10-06
申请人： Masato Koyama , Akira Nishiyama , Masamichi Suzuki , Yuuichi Kamimuta , Tsunehiro Ino
发明人： Masato Koyama , Akira Nishiyama , Masamichi Suzuki , Yuuichi Kamimuta , Tsunehiro Ino
IPC分类号： H01L29/76
CPC分类号： H01L21/823814 , H01L21/28097 , H01L21/823835 , H01L29/4975 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device can be manufactured which has a low resistance, and device characteristics of which do not vary. The semiconductor device includes a silicon layer, a gate dielectric film formed on the silicon layer, a gate electrode formed on the gate dielectric film and including a nitrided metal silicide layer which is partially crystallized, and source and drain regions formed in a surface region of the silicon layer at both sides of the gate electrode.
摘要翻译：可以制造具有低电阻的半导体器件，其器件特性不变化。半导体器件包括硅层，形成在硅层上的栅极电介质膜，形成在栅极电介质膜上的栅电极，并且包括部分结晶的氮化金属硅化物层，以及形成在栅电极两侧的硅层。

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