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81. 发明授权

US6008095A Process for formation of isolation trenches with high-K gate dielectrics 有权
标题翻译：用高K栅极电介质形成隔离沟槽的工艺
公开(公告)号：US6008095A
公开(公告)日：1999-12-28
申请号：US130766
申请日：1998-08-07
申请人： Mark I. Gardner , H. Jim Fulford , Charles E May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E May
IPC分类号： H01L21/762 , H01L21/8234 , H01L21/8242 , H01L21/70
CPC分类号： H01L21/76237 , H01L21/823481
摘要： A process for formation of isolation trenches with high-k gate dielectrics. In an example embodiment, the process comprises depositing a high permittivity layer on the substrate. An isolation trench extending from the high permittivity layer into the substrate is etched at a selected location on the substrate. The high permittivity layer is then etched to a selected thickness, and gate electrodes are formed adjacent the trench on the high permittivity layer of the selected thickness. In another embodiment, the isolation trench is formed with an oxide liner using an NO anneal, and the high-K gate dielectric layer is optionally reduced in thickness.
摘要翻译：用于形成具有高k栅极电介质的隔离沟槽的工艺。在示例性实施例中，该方法包括在衬底上沉积高介电常数层。在基板上的选定位置处蚀刻从高介电常数层延伸到衬底中的隔离沟槽。然后将高介电常数层蚀刻成所选择的厚度，并且在所选厚度的高介电常数层上与沟槽相邻地形成栅电极。在另一个实施例中，使用NO退火形成具有氧化物衬垫的隔离沟槽，并且高K栅极电介质层的厚度可选地减小。

82. 发明授权

US6005285A Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device 有权
标题翻译：用于抑制半导体器件内穿透的氩掺杂外延层
公开(公告)号：US6005285A
公开(公告)日：1999-12-21
申请号：US205321
申请日：1998-12-04
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21/205 , H01L21/336 , H01L29/10 , H01L29/167 , H01L29/32 , H01L29/36
CPC分类号： H01L29/32 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L29/105 , H01L29/1079 , H01L29/167 , H01L29/66537 , H01L29/6659
摘要： A fabrication process and transistor are described in which a transistor having decreased susceptibility to punchthrough and increased resistance to impurity diffusion is formed. One or more argon doped silicon epitaxial layers are formed superjacent a semiconductor substrate. In a preferred dual layer embodiment, a first argon doped silicon epilayer is grown over a substrate, and a second argon doped epilayer, preferably having an argon concentration less than that in the first epilayer, is formed over the first epilayer. A transistor is formed in an active region of a well having a channel laterally bounded by source/drain regions located exclusively in the second epilayer. The lighter argon doping of the second epilayer accommodates current flow in the channel while acting as a barrier to impurity outdiffusion and inhibiting punchthrough. The more heavily doped first epilayer serves primarily as a barrier to outdiffision of impurities from the bulk substrate.
摘要翻译：描述了制造工艺和晶体管，其中形成具有降低的穿透敏感性和增加的杂质扩散阻力的晶体管。在半导体衬底之上形成一个或多个氩掺杂硅外延层。在优选的双层实施例中，在衬底上生长第一氩掺杂硅外延层，并且在第一外延层上形成第二氩掺杂外延层，优选地具有比第一外延层中的氩浓度小的氩浓度。在阱的有源区中形成晶体管，该阱具有由专门位于第二外延层中的源极/漏极区横向限定的沟道。第二外延层的较轻的氩掺杂容纳通道中的电流，同时用作杂质向外扩散的屏障并抑制穿透。掺杂越多的第一外延层主要用作阻挡来自大块基板的杂质的障碍。

83. 发明授权

US6005274A Semiconductor device with a multi-level gate structure and a gate dielectric composed of barium zirconium titanate material 有权
标题翻译：具有多电平栅极结构的半导体器件和由钛酸钡锆材料构成的栅极电介质
公开(公告)号：US6005274A
公开(公告)日：1999-12-21
申请号：US163966
申请日：1998-09-30
申请人： Mark I. Gardner , Mark C. Gilmer
发明人： Mark I. Gardner , Mark C. Gilmer
IPC分类号： H01L21/28 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/28176 , H01L21/28202 , H01L21/28229 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present invention is directed to a new semiconductor device and a method for making same. The semiconductor device is comprised of a gate dielectric layer, a conductor layer, and a metal oxide layer positioned between the gate dielectric layer and the conductor layer. The method comprises forming a gate dielectric layer, a conductor layer, and a metal oxide layer between the gate dielectric layer and the conductor layer.
摘要翻译：本发明涉及一种新的半导体器件及其制造方法。该半导体器件由位于栅介电层和导体层之间的栅介电层，导体层和金属氧化物层构成。该方法包括在栅极介电层和导体层之间形成栅极电介质层，导体层和金属氧化物层。

84. 发明授权

US6004849A Method of making an asymmetrical IGFET with a silicide contact on the drain without a silicide contact on the source 失效
标题翻译：在漏极上制造具有硅化物接触的不对称IGFET的方法，而不在源极上具有硅化物接触
公开(公告)号：US6004849A
公开(公告)日：1999-12-21
申请号：US911745
申请日：1997-08-15
申请人： Mark I. Gardner , Daniel Kadosh , Michael Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael Duane
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66659 , H01L21/28114 , H01L29/665 , H01L29/7835
摘要： A method of making an asymmetrical IGFET is disclosed. The method includes providing a semiconductor substrate with an active region, wherein the active region includes a source region and a drain region, forming a gate insulator on the active region, forming a gate on the gate insulator and over the active region, implanting arsenic into the active region to provide a greater concentration of arsenic in the source region than in the drain region, growing an oxide layer over the active region, wherein the oxide layer has a greater thickness over the source region than over the drain region due to the greater concentration of arsenic in the source region than in the drain region, forming a source in the source region and a drain in the drain region, depositing a refractory metal over the gate, the source, the drain, and the oxide layer, and reacting the refractory metal with the drain without reacting the refractory metal with the source, thereby forming a silicide contact on the drain without forming a silicide contact on the source. Advantageously, the IGFET has low source-drain resistance, shallow channel junctions, and an LDD that reduces hot carrier effects.
摘要翻译：公开了制造不对称IGFET的方法。该方法包括提供具有有源区的半导体衬底，其中有源区包括源极区和漏极区，在有源区上形成栅极绝缘体，在栅极绝缘体上并在有源区上方形成栅极，将砷注入所述有源区域在所述源极区域中提供比在所述源极区域中更大的砷浓度，在所述有源区域上生长氧化物层，其中所述氧化物层在所述源极区域上比在所述漏极区域上的厚度大于所述漏极区域上的厚度在源极区域中的砷浓度比漏极区域中的砷浓度高，在源极区域形成源极，在漏极区域形成漏极，在栅极，源极，漏极和氧化物层上沉积难熔金属，并使具有漏极的难熔金属，而不使难熔金属与源极反应，从而在漏极上形成硅化物接触，而不在源上形成硅化物接触。有利地，IGFET具有低源极 - 漏极电阻，浅沟道结和降低热载流子效应的LDD。

85. 发明授权

US5994175A High performance MOSFET with low resistance design 失效
标题翻译：具有低电阻设计的高性能MOSFET
公开(公告)号：US5994175A
公开(公告)日：1999-11-30
申请号：US924781
申请日：1997-09-05
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814
摘要： A manufacturing process in which semiconductor transistors are fabricated using a fluorine or nitrogen implant into the n-channel regions and an amorphization implant to beneficially limit the spreading of the source/drain impurity distributions thereby decreasing the junction depth and increasing the sheet resistance of the source/drain regions. Broadly speaking, a gate dielectric layer is formed on a semiconductor substrate. First and second conductive gate structures are then formed on an upper surface of the gate dielectric layer. The first conductive gate is positioned over the p-well region while the second conductive gate is positioned over the n-well region. An n-channel mask is then formed on the substrate and a first impurity distribution is introduced into the p-well regions. The first impurity distribution preferably includes a species of fluorine or nitrogen. A n-type impurity distribution is then introduced into the p-well regions of the semiconductor substrate. A p-channel mask is then formed on the semiconductor substrate. After the p-channel mask is formed, a p-type impurity distribution such as boron is introduced into the n-well regions and into the second conductive gate structure. An electrically neutral impurity is then introduced into the semiconductor substrate to amorphize the semiconductor substrate to limit the subsequent redistribution of source/drain impurity distributions thereby resulting in the formation of shallow junctions. Thereafter, spacer structures are formed on sidewalls of the first and second conductive gate structures, and forming the spacer structures, n+ and p+ source/drain impurity distributions are introduced into the p and n well regions of the semiconductor substrate respectively.
摘要翻译：使用氟或氮注入到n沟道区域中制造半导体晶体管的制造工艺和非晶化注入，以有利地限制源极/漏极杂质分布的扩展，从而减小结深度并增加源极的薄层电阻 /漏区。广义地说，在半导体衬底上形成栅介质层。然后在栅介质层的上表面上形成第一和第二导电栅极结构。第一导电栅极位于p阱区上方，而第二导电栅极位于n阱区上方。然后在衬底上形成n沟道掩模，并将第一杂质分布引入p阱区。第一杂质分布优选包括一种氟或氮的种类。然后将n型杂质分布引入半导体衬底的p阱区。然后在半导体衬底上形成p沟道掩模。在形成p沟道掩模之后，诸如硼的p型杂质分布被引入n阱区并进入第二导电栅极结构。然后将电中性杂质引入半导体衬底中以使半导体衬底非晶化，以限制随后的源/漏杂质分布的再分配，从而导致形成浅结。此后，在第一和第二导电栅极结构的侧壁上形成间隔结构，并且形成间隔结构，将n +和p +源极/漏极杂质分布分别引入半导体衬底的p阱区和n阱区。

86. 发明授权

US5981363A Method and apparatus for high performance transistor devices 失效
标题翻译：高性能晶体管器件的方法和装置
公开(公告)号：US5981363A
公开(公告)日：1999-11-09
申请号：US193447
申请日：1998-11-17
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L29/51 , H01L29/78 , H01L21/3205
CPC分类号： H01L29/66659 , H01L21/2815 , H01L21/823425 , H01L21/823468 , H01L29/6656 , H01L29/7835 , H01L21/28194 , H01L21/28202 , H01L29/51 , H01L29/517 , H01L29/518 , Y10S438/947
摘要： The present invention is directed to a method for forming a semiconductor device having a reduced channel length. The method comprises forming a layer of a dielectric material above a surface of a semiconducting substrate, and forming a layer of polysilicon above the layer of dielectric material. The method further comprises forming a layer of silicon nitride or silicon oxynitride above the layer of polysilicon, and patterning said layer of polysilicon and layer of silicon nitride or silicon oxynitride to define an opening and expose a sidewall surface of the polysilicon layer. The method continues with the growth of a lateral extension of the polysilicon layer and the oxidation of the extension. The method concludes with the patterning of the polysilicon layer to define a gate conductor, and the formation of source and drain regions in the substrate.
摘要翻译：本发明涉及一种形成具有减小的通道长度的半导体器件的方法。该方法包括在半导体衬底的表面上方形成电介质材料层，以及在介电材料层之上形成多晶硅层。该方法还包括在多晶硅层之上形成氮化硅或氮氧化硅层，以及图案化所述多晶硅层和氮化硅层或氮氧化硅层以限定开口并暴露多晶硅层的侧壁表面。该方法继续扩展多晶硅层的横向延伸和延伸的氧化。该方法结束于多晶硅层的图案化以限定栅极导体，以及在衬底中形成源极和漏极区域。

87. 发明授权

US5976952A Implanted isolation structure formation for high density CMOS integrated circuits 失效
标题翻译：高密度CMOS集成电路的注入隔离结构形成
公开(公告)号：US5976952A
公开(公告)日：1999-11-02
申请号：US812320
申请日：1997-03-05
申请人： Mark I. Gardner , Mark C. Gilmer
发明人： Mark I. Gardner , Mark C. Gilmer
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76213
摘要： A semiconductor process in which oxygen is selectively implanted into isolation regions of a semiconductor substrate and subsequently annealed to form isolation structures within the isolation regions. Preferably, a semiconductor substrate is provided and a pad oxide layer is deposited on the semiconductor substrate. A barrier layer is then deposited on the pad oxide layer and a photoresist layer is formed over the barrier layer and patterned to form a photoresist mask. The photoresist mask is aligned over active regions of the semiconductor substrate. An oxygen bearing species is then introduced to an isolation region of the semiconductor substrate. The isolation region is laterally displaced between the active regions. The introducing of the oxygen bearing species into the isolation region results in the formation of an oxygenated region of the semiconductor substrate. Thereafter, the semiconductor substrate is annealed to react the oxygen bearing species with the semiconductor substrate atoms within the isolation region thereby forming an isolation oxide within the isolation region. The introduction of the oxygen bearing species into the semiconductor substrate preferably is accomplished by implanting oxygen ions into the substrate. In one embodiment the annealing of the semiconductor substrate is accomplished by immersing the semiconductor substrate in an ambient maintained at a temperature in the range of approximately 600.degree. C. to 900.degree. C. for a duration in the range of approximately 2 to 20 minutes. In another embodiment, the annealing the semiconductor substrate is accomplished during subsequent fabrication processing such that the annealing requires no dedicated processing step.
摘要翻译：一种半导体工艺，其中将氧选择性地注入到半导体衬底的隔离区域中，随后退火以在隔离区内形成隔离结构。优选地，提供半导体衬底并且在半导体衬底上沉积衬垫氧化物层。然后在衬垫氧化物层上沉积阻挡层，并在阻挡层上形成光致抗蚀剂层，并将其图案化以形成光刻胶掩模。光致抗蚀剂掩模在半导体衬底的有源区上对准。然后将含氧物质引入半导体衬底的隔离区域。隔离区域在有源区域之间横向移位。将含氧物质引入隔离区域导致半导体衬底的氧化区域的形成。此后，将半导体衬底退火以使含氧物质与隔离区域内的半导体衬底原子反应，从而在隔离区域内形成隔离氧化物。将含氧物质引入半导体衬底中优选通过将氧离子注入到衬底中来实现。在一个实施例中，半导体衬底的退火是通过将半导体衬底浸入保持在约600℃至900℃范围内的温度的环境中，持续约2至20分钟的范围来完成的。在另一个实施例中，在随后的制造处理期间完成半导体衬底的退火，使得退火不需要专门的处理步骤。

88. 发明授权

US5970331A Method of making a plug transistor 失效
标题翻译：制造插头晶体管的方法
公开(公告)号：US5970331A
公开(公告)日：1999-10-19
申请号：US3981
申请日：1998-01-07
申请人： Mark I. Gardner , Frederick N. Hause
发明人： Mark I. Gardner , Frederick N. Hause
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857
摘要： A method of making a plug transistor is disclosed. The method includes providing a semiconductor substrate with an active region of a first conductivity type, providing a doped layer of a second conductivity type in the active region, forming a dielectric layer over the active region, forming an opening in the dielectric layer, implanting a dopant of the first conductivity type through the opening into a portion of the doped layer beneath the opening thereby counterdoping the portion of the doped layer and splitting the doped layer into source and drain regions, forming a gate insulator on the active region and in the opening, and forming a gate on the gate insulator and in the opening and adjacent to the dielectric layer. Preferably, a single photoresist layer provides an etch mask for the dielectric layer and an implant mask for the dopant. It is also preferred that the gate is formed by depositing a blanket layer of gate material over the dielectric layer and into the opening and then polishing the gate material so that the gate is aligned with a top surface of the dielectric layer. In a CMOS process, the method includes forming the gate insulators and gates for the N-channel and P-channel devices separately and in sequence, and also includes forming the sources and drains for N-channel and P-channel devices before forming the gate for the P-channel device. In this manner, the N-channel and P-channel devices can have gate insulators and/or gates with different materials and/or thicknesses, and little or no boron penetration occurs, thereby providing excellent threshold voltage control.
摘要翻译：公开了一种制造插头晶体管的方法。该方法包括提供具有第一导电类型的有源区的半导体衬底，在有源区中提供第二导电类型的掺杂层，在有源区上形成电介质层，在电介质层中形成开口，第一导电类型的掺杂剂通过开口进入开口下方的掺杂层的一部分，从而对掺杂层的部分进行反掺杂并将掺杂层分裂成源区和漏区，在有源区和开口中形成栅极绝缘体并且在栅极绝缘体上和开口中形成栅极并且邻近介电层。优选地，单个光致抗蚀剂层提供用于介电层的蚀刻掩模和用于掺杂剂的注入掩模。还优选的是，通过在电介质层上沉积栅极材料的覆盖层并进入开口形成栅极，然后对栅极材料进行抛光，使得栅极与电介质层的顶表面对齐。在CMOS工艺中，该方法包括分别并且依次形成用于N沟道和P沟道器件的栅极绝缘体和栅极，并且还包括在形成栅极之前形成用于N沟道和P沟道器件的源极和漏极用于P通道设备。以这种方式，N沟道和P沟道器件可以具有不同材料和/或厚度的栅极绝缘体和/或栅极，并且很少或不发生硼渗透，由此提供优异的阈值电压控制。

89. 发明授权

US5963809A Asymmetrical MOSFET with gate pattern after source/drain formation 失效
标题翻译：源极/漏极形成后具有栅极图案的非对称MOSFET
公开(公告)号：US5963809A
公开(公告)日：1999-10-05
申请号：US883511
申请日：1997-06-26
申请人： Michael Duane , Mark I. Gardner
发明人： Michael Duane , Mark I. Gardner
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/78 , H01L21/266
CPC分类号： H01L29/66659 , H01L21/823418 , H01L29/7835
摘要： A process for fabricating a transistor in which a first impurity distribution is introduced into a semiconductor substrate prior to the formation of a conductive gate structure on the semiconductor substrate. The substrate includes a channel region disposed between a source region and an LDD region. The LDD region is laterally disposed between a channel region and a drain region. A gate dielectric layer is then formed on an upper surface of the semiconductor substrate. A conductive gate structure is then formed on an upper surface of the gate dielectric layer. A first sidewall of the conductive gate is aligned over a boundary between the source region and the channel region. A second sidewall of the conductive gate is aligned above a boundary between the channel region and the LDD region. A second impurity distribution is then implanted into the semiconductor substrate. The conductive gate structure masks the channel region during the implanting of the second impurity distribution such that the second impurity distribution is introduced into the LDD region as well as the source and drain regions of the semiconductor. An implant dose of the first implant is greater than an implant dose of the second implant such that the transistor includes a lightly doped drain region in close proximity to a drain region for reducing a maximum electric field produced within the channel region during device operation. In addition, the transistor lacks a lightly doped region in close proximity to the source region.
摘要翻译：一种制造晶体管的工艺，其中在半导体衬底上形成导电栅极结构之前将第一杂质分布引入半导体衬底。衬底包括设置在源极区域和LDD区域之间的沟道区域。 LDD区域横向设置在沟道区域和漏极区域之间。然后在半导体衬底的上表面上形成栅介质层。然后在栅介质层的上表面上形成导电栅极结构。导电栅极的第一侧壁在源极区域和沟道区域之间的边界上对准。导电栅极的第二侧壁在沟道区域和LDD区域之间的边界上方对准。然后将第二杂质分布注入到半导体衬底中。导电栅极结构在注入第二杂质分布期间掩蔽沟道区，使得第二杂质分布被引入LDD区以及半导体的源极和漏极区。所述第一注入的植入剂量大于所述第二注入的注入剂量，使得所述晶体管包括靠近漏极区的轻掺杂漏极区，用于在器件操作期间减小在所述沟道区内产生的最大电场。此外，晶体管缺乏靠近源极区域的轻掺杂区域。

90. 发明授权

US5953613A High performance MOSFET with a source removed from the semiconductor substrate and fabrication method thereof 失效
标题翻译：从半导体衬底去除源的高性能MOSFET及其制造方法
公开(公告)号：US5953613A
公开(公告)日：1999-09-14
申请号：US811415
申请日：1997-03-04
申请人： Mark I. Gardner , Frederick N. Hause
发明人： Mark I. Gardner , Frederick N. Hause
IPC分类号： H01L21/336 , H01L21/768 , H01L21/8234 , H01L23/485 , H01L29/417 , H01L29/78
CPC分类号： H01L29/66628 , H01L21/76838 , H01L21/823468 , H01L23/485 , H01L29/41775 , H01L29/41783 , H01L29/7835 , H01L2924/0002
摘要： The ultimate shallow source drain junction depth for a transistor is achieved by removing or detaching a source from the semiconductor substrate and forming an electron source on the surface of the semiconductor substrate adjacent to the transistor gate. The removal or detachment of an electron source from the semiconductor substrate eliminates the heavily-doped source drain diffusion or implant into a source region of the substrate, thereby avoiding non-uniform doping profiles that degrade long-channel subthreshold characteristics of a device as well as the punchthrough behavior of short-channel devices. A metal plug is used as an electron source which is removed or detached from the from the semiconductor substrate. The metal plug is vastly superior to doped semiconductor materials as an electron source. A method of fabricating an integrated circuit includes forming a lightly-doped drain (LDD) MOSFET structure prior to source/drain doping. The MOSFET structure includes a gate formed on a substrate over a gate oxide layer, spacers formed on sides of the gate, LDD doping of the substrate in a source region and a drain region self-aligned with the gate, and drain doping in the drain region self-aligned with the gate and spacers. The method further includes forming an oxide layer over the substrate and LDD MOSFET structure, forming a polysilicon layer over the oxide layer, cutting a via through the polysilicon layer and source layer to the substrate surface adjacent to the gate and spacer and abutting the source region of the substrate, and forming a metal plug in the via, the metal plug electrically coupling to the LDD doping in the source region of the substrate and electrically coupling to the polysilicon layer, the metal plug serving as a source for the MOSFET.
摘要翻译：通过从半导体衬底去除或分离源极并在与晶体管栅极相邻的半导体衬底的表面上形成电子源来实现晶体管的最终浅源极漏极结深度。从半导体衬底去除或分离电子源消除了重掺杂源极漏极扩散或注入到衬底的源极区域中，从而避免了劣化器件的长沟道亚阈值特性的不均匀掺杂分布，以及短通道设备的突破行为。使用金属塞作为从半导体基板去除或分离的电子源。金属插头比作为电子源的掺杂半导体材料显着优越。制造集成电路的方法包括在源极/漏极掺杂之前形成轻掺杂漏极（LDD）MOSFET结构。 MOSFET结构包括形成在栅极氧化物层上的衬底上的栅极，形成在栅极侧面的间隔物，源极区中的衬底的LDD掺杂和与栅极自对准的漏极区以及漏极中的漏极掺杂区域与栅极和间隔物自对准。该方法还包括在衬底和LDD MOSFET结构之上形成氧化物层，在氧化物层上形成多晶硅层，将通过多晶硅层和源极层的通孔切割到与栅极和间隔物相邻的衬底表面，并邻接源区并且在所述通孔中形成金属插塞，所述金属插塞电耦合到所述衬底的所述源极区域中的LDD掺杂并电耦合到所述多晶硅层，所述金属插塞用作所述MOSFET的源极。

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