专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US06872644B1 Semiconductor device with non-compounded contacts, and method of making 失效
标题翻译：具有非复合触点的半导体器件及其制造方法
公开(公告)号：US06872644B1
公开(公告)日：2005-03-29
申请号：US10126211
申请日：2002-04-19
申请人： Matthew S. Buynoski , Witold P. Maszara
发明人： Matthew S. Buynoski , Witold P. Maszara
IPC分类号： H01L21/22 , H01L21/265 , H01L21/28 , H01L21/336 , H01L21/38
CPC分类号： H01L29/66477 , H01L21/28044
摘要： A semiconductor device includes source and drain contact regions which include a non-compounded combination of a semiconductor material and at least one metal. The metal may include an elemental metal, such as gold or aluminum, or may include an intermetallic. The contact regions may be formed by depositing a limited amount of the at least one metal on a source and a drain of the device, and annealing the device to induce diffusion of the at least one metal into the source and drain. The annealing time and temperature may be selected to limit diffusion of the at least one metal.
摘要翻译：半导体器件包括源极和漏极接触区域，其包括半导体材料和至少一种金属的非复合组合。金属可以包括元素金属，例如金或铝，或者可以包括金属间化合物。接触区域可以通过在器件的源极和漏极上沉积有限量的至少一种金属而形成，并且退火该器件以诱导至少一种金属扩散到源极和漏极中。可以选择退火时间和温度来限制至少一种金属的扩散。

82. 发明授权

US06770905B1 Implantation for the formation of CuX layer in an organic memory device 失效
标题翻译：用于在有机存储器件中形成CuX层的植入
公开(公告)号：US06770905B1
公开(公告)日：2004-08-03
申请号：US10314054
申请日：2002-12-05
申请人： Matthew S. Buynoski , Suzette K. Pangrle , Sergey D. Lopatin , Minh Van Ngo
发明人： Matthew S. Buynoski , Suzette K. Pangrle , Sergey D. Lopatin , Minh Van Ngo
IPC分类号： H01L2940
CPC分类号： H01L51/0037 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L27/28 , H01L51/0035 , H01L51/0036 , H01L51/0043 , H01L51/0046 , H01L51/0048 , H01L51/0052 , H01L51/0053 , H01L51/0059 , H01L51/0062 , H01L51/0077 , H01L51/0078 , H01L51/0081 , H01L51/0085
摘要： An organic memory cell having a CuX layer made by implantation is disclosed. The organic memory cell is made of two electrodes, at least one containing copper, with a controllably conductive media between the two electrodes. The controllably conductive media contains an organic semiconductor layer and CuX layer made by implantation of a Group VIB element.
摘要翻译：公开了一种具有通过注入制造的CuX层的有机存储单元。有机存储单元由两个电极组成，至少一个电极含有铜，两个电极之间具有可控导电介质。可控导电介质包含通过注入VIB族元素制成的有机半导体层和CuX层。

83. 发明授权

US06709982B1 Double spacer FinFET formation 有权
标题翻译：双间隔FinFET形成
公开(公告)号：US06709982B1
公开(公告)日：2004-03-23
申请号：US10303702
申请日：2002-11-26
申请人： Matthew S. Buynoski , Judy Xilin An , Haihong Wang , Bin Yu
发明人： Matthew S. Buynoski , Judy Xilin An , Haihong Wang , Bin Yu
IPC分类号： H01L21311
CPC分类号： H01L29/785 , H01L21/3086 , H01L21/3088 , H01L21/32139 , H01L29/66795
摘要： A method for forming a group of structures in a semiconductor device includes forming a conductive layer on a substrate, where the conductive layer includes a conductive material, and forming an oxide layer over the conductive layer. The method further includes etching at least one opening in the oxide layer, filling the at least one opening with the conductive material, etching the conductive material to form spacers along sidewalls of the at least one opening, and removing the oxide layer and a portion of the conductive layer to form the group of structures.
摘要翻译：一种在半导体器件中形成一组结构的方法包括在基底上形成导电层，其中导电层包括导电材料，并在导电层上形成氧化物层。该方法还包括蚀刻氧化物层中的至少一个开口，用导电材料填充至少一个开口，蚀刻导电材料以在至少一个开口的侧壁上形成间隔物，并且去除氧化物层和一部分导电层形成一组结构。

84. 发明授权

US06624476B1 Semiconductor-on-insulator (SOI) substrate having selective dopant implant in insulator layer and method of fabricating 有权
标题翻译：在绝缘体层中具有选择性掺杂剂注入的绝缘体上半导体（SOI）衬底及其制造方法
公开(公告)号：US06624476B1
公开(公告)日：2003-09-23
申请号：US10134973
申请日：2002-04-29
申请人： Simon Siu-Sing Chan , Matthew S. Buynoski , Qi Xiang
发明人： Simon Siu-Sing Chan , Matthew S. Buynoski , Qi Xiang
IPC分类号： H01L2900
CPC分类号： H01L29/78603 , H01L21/84 , H01L27/1203
摘要： A semiconductor-on-insulator (SOI) device includes a buried insulator layer and an overlying semiconductor layer. Portions of the insulator layer are doped with the same dopant material, for example boron, as is in corresponding portions of the overlying surface semiconductor layer. A peak concentration of the dopant material may be located in the insulator material, or may be located in a lower portion of the surface semiconductor layer. The dopant material in the insulator layer may prevent depletion of dopant material from portions of the surface semiconductor layer, such as from channel portions of NMOS transistors.
摘要翻译：绝缘体上半导体（SOI）器件包括掩埋绝缘体层和上覆半导体层。绝缘体层的一部分用与上覆表面半导体层的相应部分中相同的掺杂剂材料（例如硼）掺杂。掺杂剂材料的峰值浓度可以位于绝缘体材料中，或者可以位于表面半导体层的下部。绝缘体层中的掺杂剂材料可以防止掺杂剂材料从表面半导体层的部分（例如从NMOS晶体管的沟道部分）的损耗。

85. 发明授权

US06376336B1 Frontside SOI gettering with phosphorus doping 有权
标题翻译：磷掺杂前面SOI吸杂
公开(公告)号：US06376336B1
公开(公告)日：2002-04-23
申请号：US09775215
申请日：2001-02-01
申请人： Matthew S. Buynoski
发明人： Matthew S. Buynoski
IPC分类号： H01L21322
CPC分类号： H01L21/3226
摘要： The present invention relates to a method of manufacturing a silicon-on-insulator semiconductor wafer, including the steps of (1) forming a silicon-on-insulator semiconductor wafer having at least one surface of a monocrystalline silicon film; (2) contacting the at least one surface with phosphorus ions to form a doped region of the monocrystalline silicon film doped with phosphorus above a region of the monocrystalline silicon film which remains undoped; (3) subjecting the wafer to conditions to getter at least one impurity from the undoped region into the doped region; and (4) removing a portion of the monocrystalline silicon film including the doped region from the at least one surface, leaving a substantial portion of the monocrystalline silicon film.
摘要翻译：本发明涉及一种制造绝缘体上硅半导体晶片的方法，包括以下步骤：（1）形成具有至少一个单晶硅膜表面的绝缘体上硅半导体晶片; （2）使所述至少一个表面与磷离子接触以在所述单晶硅膜的保留未掺杂的区域上形成掺杂有磷的单晶硅膜的掺杂区域; （3）对所述晶片进行条件以从所述未掺杂区域吸收至少一种杂质进入所述掺杂区域; 和（4）从至少一个表面去除包括掺杂区的单晶硅膜的一部分，留下大部分单晶硅膜。

86. 发明授权

US06326247B1 Method of creating selectively thin silicon/oxide for making fully and partially depleted SOI on same waffer 有权
标题翻译：产生选择性薄的硅/氧化物以在相同的干燥剂上制造完全和部分耗尽的SOI的方法
公开(公告)号：US06326247B1
公开(公告)日：2001-12-04
申请号：US09606651
申请日：2000-06-28
申请人： Srinath Krishnan , Matthew S. Buynoski
发明人： Srinath Krishnan , Matthew S. Buynoski
IPC分类号： H01L2100
CPC分类号： H01L27/1203
摘要： A method for providing partially depleted and fully depleted transistor devices on the same semiconductor wafer. A semiconductive layer is provided having an oxide layer thereon. At least one trench is then etched into the oxide layer. The oxide layer is then filled with a substrate material layer and then ground and polished down to form a generally planar upper surface. The trench filled regions of the oxide layer form an oxide layer having regions of a first thickness and the remaining regions of the oxide layer are of a second thickness. The semiconductor wafer can then be flipped and partially depleted transistor devices formed over the regions of the first thickness and fully depleted transistor devices formed over regions of the second thickness.
摘要翻译：一种用于在同一半导体晶片上提供部分耗尽和完全耗尽的晶体管器件的方法。提供其上具有氧化物层的半导体层。然后将至少一个沟槽蚀刻到氧化物层中。然后用基底材料层填充氧化物层，然后研磨并抛光，以形成大致平坦的上表面。氧化物层的沟槽填充区域形成具有第一厚度的区域的氧化物层，并且氧化物层的其余区域具有第二厚度。然后可以将半导体晶片翻转并在第二厚度的区域上形成的在第一厚度的区域上形成的部分耗尽的晶体管器件和完全耗尽的晶体管器件。

87. 发明授权

US06297157B1 Time ramped method for plating of high aspect ratio semiconductor vias and channels 有权
标题翻译：用于电镀高纵横比半导体通孔和通道的时间渐变方法
公开(公告)号：US06297157B1
公开(公告)日：2001-10-02
申请号：US09431516
申请日：1999-11-01
申请人： Sergey D. Lopatin , Matthew S. Buynoski
发明人： Sergey D. Lopatin , Matthew S. Buynoski
IPC分类号： H01L2144
CPC分类号： H01L21/2885 , C25D5/18 , C25D7/123 , H01L21/76877
摘要： A method is provided for forming conductive layers in semiconductor vias by using forward and reverse pulses during the electroplating process which have time intervals between pulses which increase with time and for forming conductive layers in semiconductor channels by using forward pulses during the electroplating process which have time intervals between pulses which also increase with time. This allows fast deposition while reducing the deposition stress to eliminate voids and speeds up the overall manufacturing process.
摘要翻译：提供了一种用于在电镀工艺期间通过使用正向和反向脉冲在电镀过程中形成导电层的方法，其间具有随时间增加的脉冲之间的时间间隔，并且通过在电镀工艺期间使用正向脉冲来形成半导体通道中的导电层，脉冲之间的间隔也随时间增加。这允许快速沉积，同时减少沉积应力以消除空隙并加速整个制造过程。

88. 发明授权

US06245658B1 Method of forming low dielectric semiconductor device with rigid, metal silicide lined interconnection system 失效
标题翻译：用刚性金属硅化物衬里互连系统形成低介电半导体器件的方法
公开(公告)号：US06245658B1
公开(公告)日：2001-06-12
申请号：US09252183
申请日：1999-02-18
申请人： Matthew S. Buynoski
发明人： Matthew S. Buynoski
IPC分类号： H01L2176
CPC分类号： H01L21/76855 , H01L21/7682 , H01L21/76852 , H01L21/76885 , H01L23/4821 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigration performance by removing the inter-layer dielectrics and supporting the interconnection system with a metal silicide lining. Embodiments include depositing a dielectric sealing layer, e.g., silicon nitride, before forming the first metallization level, removing the inter-layer dielectrics after forming the last metallization level, electroplating or electroless plating a metal, such as cobalt or nickel, to line the interconnection system, depositing a thin layer of polycrystalline silicon on the metal, heating to form the metal silicide lining on the interconnection system, and forming dielectric protective layers, e.g. a silane derived oxide bottommost protective layer, on the uppermost metallization level.
摘要翻译：通过去除层间电介质并用金属硅化物衬里支撑互连系统，多级半导体器件形成具有减小的寄生电容，而不牺牲结构完整性或电迁移性能。实施例包括在形成第一金属化水平之前沉积电介质密封层，例如氮化硅，在形成最后的金属化水平之后去除层间电介质，电镀或化学镀金属（例如钴或镍）以使互连系统，在金属上沉积薄层的多晶硅，加热以在互连系统上形成金属硅化物衬里，并形成介电保护层，例如硅烷衍生的氧化物最底层的保护层，最上层的金属化层。

89. 发明授权

US06180441B2 Bar field effect transistor 有权
标题翻译：棒场效应晶体管
公开(公告)号：US06180441B2
公开(公告)日：2001-01-30
申请号：US09307698
申请日：1999-05-10
申请人： John T. Yue , Matthew S. Buynoski , Yowjuang W. Liu , Peng Fang
发明人： John T. Yue , Matthew S. Buynoski , Yowjuang W. Liu , Peng Fang
IPC分类号： H01L21336
CPC分类号： H01L29/66636 , B82Y10/00 , H01L21/26586 , H01L29/41766 , H01L29/66439 , H01L29/66575 , H01L29/66621 , H01L29/66795 , H01L29/785 , H01L29/7853 , H01L29/7854
摘要： A field effect transistor is formed across a one or more trenches (26) or bars (120), thereby increasing the effective width of the channel region and the current-carrying capacity of the device.
摘要翻译：在一个或多个沟槽（26）或条（120）上形成场效应晶体管，从而增加了沟道区的有效宽度和器件的载流能力。

90. 发明授权

US5864160A Transistor device with reduced hot carrier injection effects 失效
标题翻译：具有减少热载流子注入效应的晶体管器件
公开(公告)号：US5864160A
公开(公告)日：1999-01-26
申请号：US653147
申请日：1996-05-24
申请人： Matthew S. Buynoski
发明人： Matthew S. Buynoski
IPC分类号： H01L21/28 , H01L21/336 , H01L29/51 , H01L29/76 , H01L23/62
CPC分类号： H01L29/512 , H01L21/28167 , H01L29/4991 , H01L29/515 , H01L29/66575
摘要： A MOS transistor includes a void space as part of the gate oxide layer on the drain end of the transistor. The void space replaces a region of the gate oxide layer so that no oxide is present for injection of hot carriers. The presence of the void space, preferably containing a vacuum, also reduces the total gate capacitance of the device. The void space is formed by chemical etching of the gate oxide layer and void space sealing during device manufacture.
摘要翻译： MOS晶体管包括作为晶体管的漏极端上的栅极氧化物层的一部分的空隙空间。空隙空间取代了栅极氧化物层的区域，使得不存在用于注入热载流子的氧化物。优选含有真空的空隙空间的存在也降低了器件的总栅极电容。在器件制造期间通过化学蚀刻栅极氧化物层和空隙空间密封形成空隙空间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式