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81. 发明授权

US08627053B2 Method and apparatus for secure execution using a secure memory partition 有权
标题翻译：使用安全存储器分区进行安全执行的方法和装置
公开(公告)号：US08627053B2
公开(公告)日：2014-01-07
申请号：US12977468
申请日：2010-12-23
申请人： Millind Mittal
发明人： Millind Mittal
IPC分类号： G06F9/24 , G06F9/40
CPC分类号： G06F21/72 , G06F12/1408 , G06F12/1441 , G06F12/1491 , G06F21/60 , G06F21/602 , G06F21/78 , G06F2221/2107 , G06F2221/2125
摘要： A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.
摘要翻译：能够安全执行的处理器。该处理器包含一个执行单元和安全的分区逻辑，将分区保存在内存中。处理器还包含耦合到执行单元的加密逻辑，其加密和解密安全数据和代码。

82. 发明授权

US08499012B1 System and method for attached storage stacking 有权
标题翻译：连接存储堆放的系统和方法
公开(公告)号：US08499012B1
公开(公告)日：2013-07-30
申请号：US12818870
申请日：2010-06-18
申请人： Millind Mittal
发明人： Millind Mittal
IPC分类号： G06F12/00 , G06F17/30 , G06F7/00
CPC分类号： H04L67/1097
摘要： A system and method are provided for stacking storage drives in a network attached storage (NAS) system. The method provides a NAS stacking network including at least a first and second stackable building block (SBB), where each SBB includes a head, with an embedded processor and storage application, and a storage drive including client files. The method connects a first interface of the first SBB to a client computer device via a LAN switch, and connects a second interface of the first SBB to the first interface of the second SBB. A directory is built of client files stored in the first and second SBBs. The directory is maintained in both the first and second SBBs. In one aspect, the first SBB, acting as a primary SBB, provides access to NAS stacking network directory structure in response to an inquiry from a client computer connected to the LAN switch.
摘要翻译：提供了一种用于将存储驱动器堆叠在网络连接存储（NAS）系统中的系统和方法。该方法提供包括至少第一和第二可堆叠构建块（SBB）的NAS堆叠网络，其中每个SBB包括具有嵌入式处理器和存储应用的头部以及包括客户端文件的存储驱动器。该方法通过LAN交换机将第一SBB的第一接口连接到客户端计算机设备，并将第一SBB的第二接口连接到第二SBB的第一接口。目录由存储在第一和第二SBB中的客户端文件构建。该目录保持在第一和第二SBB中。在一个方面，作为主SBB的第一SBB响应于来自连接到LAN交换机的客户端计算机的查询，提供对NAS堆叠网络目录结构的访问。

83. 发明授权

US08488618B1 Dual-connect service box with router bypass 有权
标题翻译：双路服务器与路由器旁路
公开(公告)号：US08488618B1
公开(公告)日：2013-07-16
申请号：US12769540
申请日：2010-04-28
申请人： Millind Mittal , Robert James Fanfelle
发明人： Millind Mittal , Robert James Fanfelle
IPC分类号： H04L12/28
CPC分类号： H04L63/02 , H04L63/0236
摘要： A system and method provide both inline services and in-network services for a dual-connect service box interposed between a modem and a router. The method transceives communications between a service box wide area network (WAN) port and a local area network (LAN) port of a WAN-connected broadband modem, and between a service box WAN-proxy port and a WAN port of a router. The method also selectively transceives communications between the service box WAN port and a LAN port. A service box binding module monitors messages transceived between the router and the modem to determine the service box WAN IP address, and registers at least one service box WAN IP addresses with a WAN network-connected account server. The method selectively transceives communications in response to an authentification means, which may be identifying an authorized port number in the communications, or identifying an authorized command in the communications.
摘要翻译：系统和方法为插入在调制解调器和路由器之间的双连接服务盒提供内联服务和网络内服务。该方法收发WAN连接宽带调制解调器的服务盒广域网（WAN）端口和局域网（LAN）端口之间以及路由器的服务盒WAN代理端口和WAN端口之间的通信。该方法还选择性地收发服务盒WAN端口和LAN端口之间的通信。服务箱绑定模块监视路由器和调制解调器之间收发的消息，以确定服务箱WAN IP地址，并向WAN网络连接的帐户服务器注册至少一个服务箱WAN IP地址。所述方法响应于认证装置选择性地收发通信，所述认证装置可能是识别通信中的授权端口号，或者识别通信中的授权命令。

84. 发明授权

US08347072B2 Method and apparatus for secure execution using a secure memory partition 有权
公开(公告)号：US08347072B2
公开(公告)日：2013-01-01
申请号：US12977459
申请日：2010-12-23
申请人： Millind Mittal
发明人： Millind Mittal
IPC分类号： G06F9/00 , H04L9/32
CPC分类号： G06F21/72 , G06F12/1408 , G06F12/1441 , G06F12/1491 , G06F21/60 , G06F21/602 , G06F21/78 , G06F2221/2107 , G06F2221/2125
摘要： A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

85. 发明申请

US20090024643A1 Multi-Level Compressed Look-up Tables Formed by Logical Operations to Compress Selected Index Bits 有权
标题翻译：通过逻辑操作形成的多级压缩查找表来压缩所选择的索引位
公开(公告)号：US20090024643A1
公开(公告)日：2009-01-22
申请号：US12190692
申请日：2008-08-13
申请人： Millind Mittal
发明人： Millind Mittal
IPC分类号： G06F17/30
CPC分类号： G06F17/30961 , Y10S707/99942 , Y10S707/99943
摘要： A lookup is performed using multiple levels of compressed stride tables in a multi-bit Trie structure. An input lookup key is divided into several strides including a current stride of S bits. A valid entry in a current stride table is located by compressing the S bits to form a compressed index of D bits into the current stride table. A compression function logically combines the S bits to generate the D compressed index bits. An entry in a prior-level table points to the current stride table and has a field indicating which compression function and mask to use. Compression functions can include XOR, shifts, rotates, and multi-bit averaging. Rather than store all 2S entries, the current stride table is compressed to store only 2D entries. Ideally, the number of valid entries in the current stride table is between 2D−1 and 2D for maximum compression. Storage requirements are reduced.
摘要翻译：在多位Trie结构中使用多级压缩步幅表进行查找。输入查找键被分成包括S位的当前步幅的几个步骤。通过压缩S位来形成当前步幅表中的有效条目，以形成D位的压缩索引到当前步幅表中。压缩函数逻辑组合S位以产生D压缩索引位。前一级表中的条目指向当前步幅表，并具有指示要使用的压缩函数和掩码的字段。压缩功能可以包括XOR，移位，旋转和多位平均。而不是存储所有2S条目，当前步幅表被压缩以仅存储2D条目。理想情况下，当前步幅表中有效条目的数量在2D-1和2D之间用于最大压缩。存储要求降低。

86. 发明授权

US07194634B2 Attestation key memory device and bus 有权
标题翻译：证明密钥存储设备和总线
公开(公告)号：US07194634B2
公开(公告)日：2007-03-20
申请号：US09672602
申请日：2001-02-26
申请人： Carl M. Ellison , Roger A. Golliver , Howard C. Herbert , Derrick C. Lin , Francis X. McKeen , Gilbert Neiger , Ken Reneris , James A. Sutton , Shreekant S. Thakkar , Millind Mittal
发明人： Carl M. Ellison , Roger A. Golliver , Howard C. Herbert , Derrick C. Lin , Francis X. McKeen , Gilbert Neiger , Ken Reneris , James A. Sutton , Shreekant S. Thakkar , Millind Mittal
IPC分类号： G06F11/30
CPC分类号： G06F12/1491 , G06F21/57 , G06F2221/2105
摘要： In an embodiment of the present invention, a technique is provided for remote attestation. An interface maps a device via a bus to an address space of a chipset in a secure environment for an isolated execution mode. The secure environment is associated with an isolated memory area accessible by at least one processor. The at least one processor operates in one of a normal execution mode and the isolated execution mode. A communication storage corresponding to the address space allows the device to exchange security information with the at least one processor in the isolated execution mode in a remote attestation.
摘要翻译：在本发明的实施例中，提供了用于远程证明的技术。接口将设备通过总线映射到安全环境中的芯片组的地址空间，用于隔离执行模式。安全环境与由至少一个处理器可访问的隔离存储器区域相关联。所述至少一个处理器以正常执行模式和隔离执行模式之一进行操作。对应于地址空间的通信存储器允许设备在远程证明中以隔离执行模式与至少一个处理器交换安全信息。

87. 发明申请

US20060206943A1 Protecting software environment in isolated execution 有权
标题翻译：在孤立执行中保护软件环境
公开(公告)号：US20060206943A1
公开(公告)日：2006-09-14
申请号：US11386269
申请日：2006-03-21
申请人： Carl Ellison , Roger Golliver , Howard Herbert , Derrick Lin , Francis McKeen , Gilbert Neiger , Ken Reneris , James Sutton , Shreekant Thakkar , Millind Mittal
发明人： Carl Ellison , Roger Golliver , Howard Herbert , Derrick Lin , Francis McKeen , Gilbert Neiger , Ken Reneris , James Sutton , Shreekant Thakkar , Millind Mittal
IPC分类号： H04N7/16
CPC分类号： G06F21/53 , G06F9/468 , G06F21/562 , G06F21/57 , G06F21/74 , G06F2221/2105
摘要： A processing system has a processor that can operate in a normal ring 0 operating mode and one or more higher ring operating modes above the normal ring 0 operating mode. In addition, the processor can operate in an isolated execution mode. A memory in the processing system may include an ordinary memory area that can be accessed from the normal ring 0 operating mode, as well as an isolated memory area that can be accessed from the isolated execution mode but not from the normal ring 0 operating mode. The processing system may also include an operating system (OS) nub, as well as a key generator. The key generator may generate an OS nub key (OSNK) based at least in part on an identification of the OS nub and a master binding key (BK0) of the platform. Other embodiments are described and claimed.
摘要翻译：处理系统具有处理器，该处理器可以在正常环0操作模式和高于正常环0操作模式的一个或多个较高环操作模式下操作。此外，处理器可以在隔离的执行模式下操作。处理系统中的存储器可以包括可以从正常环0操作模式访问的普通存储器区域以及可以从隔离执行模式而不是从正常环0操作模式访问的隔离存储器区域。处理系统还可以包括操作系统（OS）nub以及密钥生成器。密钥生成器可以至少部分地基于OS nub的标识和平台的主绑定密钥（BK 0）来生成OS nub密钥（OSNK）。描述和要求保护其他实施例。

88. 发明授权

US06754815B1 Method and system for scrubbing an isolated area of memory after reset of a processor operating in isolated execution mode if a cleanup flag is set 有权
标题翻译：如果设置了清除标志，则在分离执行模式下操作的处理器复位后，擦除存储器隔离区域的方法和系统
公开(公告)号：US06754815B1
公开(公告)日：2004-06-22
申请号：US09618659
申请日：2000-07-18
申请人： Carl M. Ellison , Roger A. Golliver , Howard C. Herbert , Derrick C. Lin , Francis X. McKeen , Gilbert Neiger , Ken Reneris , James A. Sutton , Shreekant S. Thakkar , Millind Mittal
发明人： Carl M. Ellison , Roger A. Golliver , Howard C. Herbert , Derrick C. Lin , Francis X. McKeen , Gilbert Neiger , Ken Reneris , James A. Sutton , Shreekant S. Thakkar , Millind Mittal
IPC分类号： G06F15177
CPC分类号： G06F21/74 , G06F9/4401 , G06F21/62 , G06F2221/2143
摘要： The present invention provides a method, apparatus, and system for invoking a reset process in response to a processor being individually reset. The reset processor operates within a platform in an isolated execution mode and is associated with an isolated area of memory. An initialization process is invoked for an initializing processor. The initialization process determines whether or not a cleanup flag is set. If the cleanup flag is set, the isolated area of memory is scrubbed. In one embodiment, when a last processor operating in the platform is reset, it is reset without clearing the cleanup flag. Subsequently, an initializing processor invokes the initialization process. The initialization process determines that the cleanup flag is set. The initialization process invokes the execution of a processor nub loader. If the cleanup flag is set, the processor nub loader scrubs the isolated area of memory and invokes a controlled close for the initializing processor. The controlled close clears the cleanup flag. The initializing processor then re-performs the initialization process. Upon the second iteration of the initialization process, with the cleanup flag not set, a new isolated area of memory is created for the initializing processor.
摘要翻译：本发明提供了一种响应于处理器被单独复位来调用复位过程的方法，装置和系统。复位处理器在孤立执行模式的平台内运行，并与存储器的隔离区域相关联。初始化处理器调用初始化过程。初始化过程确定是否设置清除标志。如果清除标志置位，则清除隔离区的内存。在一个实施例中，当在平台中操作的最后一个处理器被重置时，它被重置而不清除清除标志。随后，初始化处理器调用初始化过程。初始化过程确定清除标志被设置。初始化过程调用处理器nub加载器的执行。如果清除标志置位，则处理器nub加载器将擦除存储器的隔离区域，并为初始化处理器调用受控关闭。受控关闭清除清除标志。初始化处理器然后重新执行初始化过程。在初始化过程的第二次迭代时，在清除标志未设置的情况下，为初始化处理器创建一个新的隔离区域。

89. 发明授权

US5860126A Controlling shared memory access ordering in a multi-processing system using an acquire/release consistency model 失效
标题翻译：使用获取/释放一致性模型控制多处理系统中的共享内存访问排序
公开(公告)号：US5860126A
公开(公告)日：1999-01-12
申请号：US768775
申请日：1996-12-17
申请人： Millind Mittal
发明人： Millind Mittal
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46 , G06F12/00
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087
摘要： A technique for controlling memory access ordering in a multi-processing system in which a sequence of accesses to acquire, access and release a shared space of memory is strictly adhered to by use of two specialized instructions for controlling memory access. Two instructions noted as MFDA (Memory Fence Directional--Acquire)and MFDR (Memory Fence Directional--Release) are utilized to control the ordering. The MFDA instruction when encountered in a program operates to ensure that all previous accesses to the specified address (typically to a lock controlling access to the shared space) become visible to other processors before all future accesses are permitted. The MFDR instruction when encountered in a program operates to ensure that all previous accesses become visible to other processors before any future accesses to the specified address. The accesses to the shared space of memory are then located between the MFDA and MFDR instructions and made visible to the other processors in proper order with respect to accesses for acquiring and releasing the shared space.
摘要翻译：一种用于在多处理系统中控制存储器访问排序的技术，其中通过使用用于控制存储器访问的两个专用指令严格地遵守用于获取，访问和释放存储器的共享空间的访问序列。被指定为MFDA（记忆栅栏方向获取）和MFDR（记忆栅栏定向释放）的两个指令用于控制排序。在程序中遇到MFDA指令时，可以确保在允许所有未来访问之前，所有之前对指定地址的访问（通常是控制对共享空间的访问锁）在其他处理器中可见。程序中遇到的MFDR指令运行，以确保所有以前的访问在任何将来访问指定地址之前变得对其他处理器可见。然后，对存储器的共享空间的访问位于MFDA和MFDR指令之间，并且对于其他处理器，对于获取和释放共享空间的访问，以适当的顺序可见。

90. 发明授权

US5787026A Method and apparatus for providing memory access in a processor pipeline 失效
标题翻译：用于在处理器流水线中提供存储器访问的方法和装置
公开(公告)号：US5787026A
公开(公告)日：1998-07-28
申请号：US575780
申请日：1995-12-20
申请人： Doron Orenstein , Millind Mittal , Ofri Wechsler
发明人： Doron Orenstein , Millind Mittal , Ofri Wechsler
IPC分类号： G06F9/38 , G06F9/302
CPC分类号： G06F9/3826 , G06F9/3867
摘要： The invention provides a method and apparatus for providing operand reads in a processor pipeline. According to one aspect of the invention, a method is described for executing an instruction in a computer pipeline that requires different operands be read from the same register file in different stages of the computer pipeline. According to another aspect of the invention, a method is described for executing an instruction in a processor pipeline. According to this method, at least a first operand is read from a register file in a first stage of the processor pipeline. If execution of the instruction causes the processor to place the first operand in a storage area other than the register file, then the first operand in written to that storage area in a subsequent stage of the processor pipeline. Otherwise, one or more ALU operations are performed on the first operand and at least a second operand in a different subsequent stage of the processor pipeline.
摘要翻译：本发明提供了一种用于在处理器管线中提供操作数读取的方法和装置。根据本发明的一个方面，描述了一种用于执行计算机流水线中的指令的方法，其需要在计算机管线的不同阶段从同一寄存器文件读取不同的操作数。根据本发明的另一方面，描述了一种用于在处理器流水线中执行指令的方法。根据该方法，在处理器管线的第一级中，从寄存器文件读取至少第一操作数。如果指令的执行导致处理器将第一操作数放置在除寄存器文件之外的存储区域中，则将第一操作数写入处理器管线的后续阶段中的该存储区域。否则，在处理器流水线的不同后续阶段的第一操作数和至少第二操作数上执行一个或多个ALU操作。

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