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81. 发明申请

US20090198914A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD IN WHICH AN INTERCONNECT OPERATION INDICATES ACCEPTABILITY OF PARTIAL DATA DELIVERY 有权
标题翻译：数据处理系统，互连操作的处理器和方法显示部分数据传送的接受性
公开(公告)号：US20090198914A1
公开(公告)日：2009-08-06
申请号：US12024467
申请日：2008-02-01
申请人： LAKSHMINARAYANA B. ARIMILLI , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
发明人： LAKSHMINARAYANA B. ARIMILLI , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0886 , G06F2212/1016
摘要： According to at least one embodiment, a method of data processing in a multiprocessor data processing system includes a requesting processing unit initiating an interconnect operation including a memory access request that indicates an acceptability of a variable amount of data to service the interconnect request for data. In response to snooping the memory access request on an interconnect, a snooper selects an amount of data to supply to the requesting processing unit and transmits the selected amount of data to the requesting processing unit. The requesting processing unit receives the selected amount of data and utilizes at least some of the selected amount of data to service a processor request.
摘要翻译：根据至少一个实施例，多处理器数据处理系统中的数据处理方法包括请求处理单元发起包括存储器访问请求的互连操作，所述存储器访问请求指示可变数量的数据的可接受性来维护数据的互连请求。响应于在互连上窥探存储器访问请求，窥探者选择要提供给请求处理单元的数据量，并将所选择的数据量发送到请求处理单元。请求处理单元接收所选择的数据量并利用所选择的数量的数据中的至少一些来处理处理器请求。

82. 发明申请

US20100070717A1 Techniques for Cache Injection in a Processor System Responsive to a Specific Instruction Sequence 失效
标题翻译：针对特定指令序列的处理器系统中缓存注入的技术
公开(公告)号：US20100070717A1
公开(公告)日：2010-03-18
申请号：US12212961
申请日：2008-09-18
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/08 , G06F13/28 , G06F12/00
CPC分类号： G06F12/0862 , G06F12/0831 , G06F12/0897 , G06F2212/6024
摘要： A technique for performing cache injection includes monitoring an instruction stream for a specific instruction sequence. Addresses on a bus are then monitored, at a cache, in response to detecting the specific instruction sequence a determined number of times. Ownership of input/output data on the bus is then acquired by the cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache.
摘要翻译：用于执行高速缓存注入的技术包括监视特定指令序列的指令流。响应于检测到特定指令序列确定的次数，在总线上的地址被监视在高速缓存。当总线上的地址（与输入/输出数据相关联）对应于存储在高速缓存中的数据块的地址时，总线上的输入/输出数据的所有权由高速缓存获取。

83. 发明申请

US20090198958A1 System and Method for Performing Dynamic Request Routing Based on Broadcast Source Request Information 有权
标题翻译：基于广播源请求信息执行动态请求路由的系统和方法
公开(公告)号：US20090198958A1
公开(公告)日：2009-08-06
申请号：US12024553
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
IPC分类号： G06F13/14 , G06F9/02
CPC分类号： H04L45/122 , H04L45/06
摘要： A system and method for performing dynamic request routing based on broadcast source request information are provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide source request information to each of the other processor chips in the system. The source request information identifies the number of active source requests sent by the processor chip that originated the heartbeat signal. The source request information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data.
摘要翻译：提供了一种基于广播源请求信息进行动态请求路由的系统和方法。系统中的每个处理器芯片可以使用其产生的同步心跳信号来向系统中的每个其他处理器芯片提供源请求信息。源请求信息标识由发起心跳信号的处理器芯片发送的活动源请求的数量。来自系统中的每个处理器芯片的源请求信息可被处理器芯片用于确定用于从源处理器芯片到目的地处理器芯片的数据的最佳路由路径。结果，当选择哪个处理器芯片来转发数据时，可以考虑在每个可能的路由路径处的每个处理器芯片处理数据的拥塞。

84. 发明授权

US07827428B2 System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture 有权
标题翻译：用于在多层全图互连架构中提供集群范围的系统时钟的系统
公开(公告)号：US07827428B2
公开(公告)日：2010-11-02
申请号：US11848440
申请日：2007-08-31
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
IPC分类号： G06F1/00 , G06F1/04 , G06F1/12
CPC分类号： G06F1/12 , H04J3/0685 , H04Q2213/13092 , H04Q2213/13214 , H04Q2213/13322 , H04Q2213/1336
摘要： A system for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.
摘要翻译：提供了一种用于在多层全图（MTFG）互连架构中提供集群范围的系统时钟的系统。计算群集中的每个处理器芯片发送的心跳信号同步。基于同步的心跳信号，在每个处理器芯片中产生内部系统时钟信号。结果，每个处理器芯片的内部系统时钟信号被同步，因为作为内部系统时钟信号的基础的心跳信号被同步。提供了用于使用同一处理器书中的处理器芯片的直接耦合，同一超级节点中的不同处理器书以及MTFG互连体系结构的不同超节点中的不同处理器簿来执行这种同步的机制。

85. 发明申请

US20090198912A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD FOR IMPLEMENTING CACHE MANAGEMENT FOR PARTIAL CACHE LINE OPERATIONS 有权
标题翻译：数据处理系统，用于执行部分缓存线路操作的高速缓存管理的处理器和方法
公开(公告)号：US20090198912A1
公开(公告)日：2009-08-06
申请号：US12024447
申请日：2008-02-01
申请人： LAKSHMINARAYANA B. ARIMILLI , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
发明人： LAKSHMINARAYANA B. ARIMILLI , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F12/0831 , G06F12/0837 , G06F12/0886
摘要： A method of data processing in a cache memory includes caching a plurality of cache lines of data in a corresponding plurality of entries in a cache array, where each of the plurality of cache lines includes multiple data granules. For each of the plurality of cache entries, a plurality of line coherency state fields indicates an associated coherency state applicable to two or more data granules. For at least a particular cache line among the plurality of cache lines, a granule coherency state field indicates a coherency state for a particular granule of the multiple data granules in the particular cache line, where the coherency state field indicated by the granule coherency state field differs from that indicated for the particular cache line by its line coherency state field.
摘要翻译：高速缓冲存储器中的数据处理方法包括：高速缓存阵列中的相应多个条目中的多条高速缓存行数据缓存，其中多个高速缓存行中的每一条包括多个数据粒子。对于多个高速缓存条目中的每一个，多个行相关性状态字段指示适用于两个或更多个数据粒子的相关联的一致性状态。对于多个高速缓存行中的至少一个特定高速缓存行，颗粒一致性状态字段指示特定高速缓存行中的多个数据颗粒的特定颗粒的一致性状态，其中由颗粒一致性状态字段指示的一致性状态字段与特定高速缓存行通过其行一致性状态字段指示的不同。

86. 发明申请

US20090070617A1 Method for Providing a Cluster-Wide System Clock in a Multi-Tiered Full-Graph Interconnect Architecture 有权
标题翻译：在多层全图互连架构中提供集群宽系统时钟的方法
公开(公告)号：US20090070617A1
公开(公告)日：2009-03-12
申请号：US11853522
申请日：2007-09-11
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
IPC分类号： G06F1/12
CPC分类号： G06F1/10 , G06F1/12
摘要： A method for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.
摘要翻译：提供了一种在多层全图（MTFG）互连架构中提供集群范围的系统时钟的方法。计算群集中的每个处理器芯片发送的心跳信号同步。基于同步的心跳信号，在每个处理器芯片中产生内部系统时钟信号。结果，每个处理器芯片的内部系统时钟信号被同步，因为作为内部系统时钟信号的基础的心跳信号被同步。提供了用于使用同一处理器书中的处理器芯片的直接耦合，同一超级节点中的不同处理器书以及MTFG互连体系结构的不同超节点中的不同处理器簿来执行这种同步的机制。

87. 发明授权

US09110885B2 Techniques for cache injection in a processor system 有权
标题翻译：在处理器系统中缓存注入的技术
公开(公告)号：US09110885B2
公开(公告)日：2015-08-18
申请号：US12212917
申请日：2008-09-18
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/00 , G06F13/28 , G06F12/08
CPC分类号： G06F13/28 , G06F12/0835 , G06F2212/507 , G06F2212/621
摘要： A technique for performing cache injection includes monitoring addresses on a bus. Ownership of input/output data on the bus is acquired by a cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache.
摘要翻译：执行高速缓存注入的技术包括监视总线上的地址。当总线上的地址（与输入/输出数据相关联）对应于存储在高速缓存中的数据块的地址时，通过高速缓存获取总线上的输入/输出数据的所有权。

88. 发明授权

US08255635B2 Claiming coherency ownership of a partial cache line of data 有权
标题翻译：声称部分高速缓存行数据的一致性所有权
公开(公告)号：US08255635B2
公开(公告)日：2012-08-28
申请号：US12024392
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
IPC分类号： G06F12/04
CPC分类号： G06F12/0831
摘要： According to method of data processing in a multiprocessor data processing system, in response to a processor request to modify a target granule of a target cache line of data containing multiple granules, a processing unit originates on an interconnect of the multiprocessor data processing system a data-claim-partial request that requests permission to promote only the target granule of the target cache line to a unique copy with an intent to modify the target granule. In response to a combined response to the data-claim-partial request indicating success (the combined response representing a system-wide response to the data-claim-partial-request), the processing unit promotes only the target granule of the target cache line to a unique copy by updating a coherency state of the target granule and retaining a coherency state of at least one other granule of the target cache line.
摘要翻译：根据多处理器数据处理系统中的数据处理方法，响应于修改目标高速缓存行数据包含多个粒子的处理器请求，处理单元在多处理器数据处理系统的互连上产生数据 - 要求 - 部分请求，请求仅将目标缓存行的目标颗粒推广到具有修改目标颗粒的唯一副本的权限。响应于表示成功的数据声明部分请求的组合响应（表示对数据声明部分请求的系统范围响应的组合响应），处理单元仅促进目标高速缓存行的目标颗粒通过更新目标颗粒的相关性状态并保持目标高速缓存行的至少一个其他颗粒的一致性状态来发送到唯一的副本。

89. 发明授权

US08117401B2 Interconnect operation indicating acceptability of partial data delivery 有权
标题翻译：互连操作指示部分数据传送的可接受性
公开(公告)号：US08117401B2
公开(公告)日：2012-02-14
申请号：US12024467
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0886 , G06F2212/1016
摘要： According to at least one embodiment, a method of data processing in a multiprocessor data processing system includes a requesting processing unit initiating an interconnect operation including a memory access request that indicates an acceptability of a variable amount of data to service the interconnect request for data. In response to snooping the memory access request on an interconnect, a snooper selects an amount of data to supply to the requesting processing unit and transmits the selected amount of data to the requesting processing unit. The requesting processing unit receives the selected amount of data and utilizes at least some of the selected amount of data to service a processor request.
摘要翻译：根据至少一个实施例，多处理器数据处理系统中的数据处理方法包括请求处理单元发起包括存储器访问请求的互连操作，所述存储器访问请求指示可变数量的数据的可接受性来维护数据的互连请求。响应于在互连上窥探存储器访问请求，窥探者选择要提供给请求处理单元的数据量，并将所选择的数据量发送到请求处理单元。请求处理单元接收所选择的数据量并利用所选择的数量的数据中的至少一些来处理处理器请求。

90. 发明授权

US08077602B2 Performing dynamic request routing based on broadcast queue depths 失效
标题翻译：基于广播队列深度执行动态请求路由
公开(公告)号：US08077602B2
公开(公告)日：2011-12-13
申请号：US12024514
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
IPC分类号： G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26 , H04L12/28 , H04L12/56
CPC分类号： G06F15/17
摘要： Mechanisms for performing dynamic request routing based on broadcast depth queue information are provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide queue depth information to each of the other processor chips in the system. The queue depth information identifies a number of requests or amount of data in each of the queues of a processor chip that originated the heartbeat signal. The queue depth information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data.
摘要翻译：提供了基于广播深度队列信息执行动态请求路由的机制。系统中的每个处理器芯片可以使用其产生的同步心跳信号来向系统中的每个其他处理器芯片提供队列深度信息。队列深度信息识别发起心跳信号的处理器芯片的每个队列中的数量的请求或数据量。系统中每个处理器芯片的队列深度信息可被处理器芯片用于确定用于从源处理器芯片到目的地处理器芯片的数据的最佳路由路径。结果，当选择哪个处理器芯片来转发数据时，可以考虑在每个可能的路由路径处的每个处理器芯片处理数据的拥塞。

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